METHOD AND MEANS FOR CLASSIFYING DATA PACKET

    公开(公告)号:JP2001274837A

    公开(公告)日:2001-10-05

    申请号:JP2001015820

    申请日:2001-01-24

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To classify a packet to be processed about an applicable rule or other data items in response to a plurality of decision reference values included in each packet. SOLUTION: A range token with a nonuniform length is allocated to a reference range of a decision reference value, and as a result, each combination of input values from a packet can be represented by a specific variable length combination of range tokens. A retrieval tree including a stored rule ID is designed so that each combination of specific range tokens used as an input of a longest match prefix lookup operation can supply a necessary ID. A combination of different range tokens having the same prefix can use the same path to one stored rule ID, as a result, the storage area requirement and the time requirement of a classification procedure are reduced in this method, and simple update at a time when rules are changed can be performed.

    METHOD AND APPARATUS FOR INTERMEDIATE BUFFER SEGMENTATION AND REASSEMBLY
    2.
    发明申请
    METHOD AND APPARATUS FOR INTERMEDIATE BUFFER SEGMENTATION AND REASSEMBLY 审中-公开
    用于中间缓冲器分割和重新组合的方法和装置

    公开(公告)号:WO2004049179A3

    公开(公告)日:2004-07-29

    申请号:PCT/IB0305016

    申请日:2003-11-05

    CPC classification number: G06F13/385 G06F13/28

    Abstract: The present invention discloses a method and apparatus for transmitting incoming packet data via a data bus to a memory unit and transmitting outgoing packet data from the memory unit to a communication link via the data bus. The method for transmitting packet data via a data bus to a memory unit comprises the steps of receiving a stream of packet data; storing the received packet data in a buffer unit; and in response to the stored packet data, transmitting a burst of packet data to the memory unit, wherein the size of the burst of packet data depends on the properties of the data bus. The method for transmitting outgoing packet data from a memory unit to a communication link via a data bus comprises the steps of transmitting a burst of packet data from the memory unit to a buffer unit, wherein the size of the burst of packet data depends on the properties of the data bus; storing the packet data in the buffer unit; segmenting the packet data in the buffer; and in response to the transmission step, sending the segmented packet data to the communication link.

    Abstract translation: 本发明公开了一种用于经由数据总线将输入分组数据发送到存储单元并且经由数据总线将输出分组数据从存储单元发送到通信链路的方法和设备。 经由数据总线将分组数据传输到存储器单元的方法包括以下步骤:接收分组数据流; 将接收的分组数据存储在缓冲器单元中; 并且响应于所存储的分组数据,将分组数据突发发送到存储器单元,其中分组数据突发的大小取决于数据总线的属性。 用于经由数据总线将输出分组数据从存储器单元发送到通信链路的方法包括以下步骤:将分组数据的突发从存储器单元发送到缓冲器单元,其中分组数据的突发的大小取决于 数据总线的属性; 将分组数据存储在缓冲器单元中; 将分组数据分段到缓冲器中; 并且响应于传输步骤,将分段的分组数据发送到通信链路。

    3.
    发明专利
    未知

    公开(公告)号:DE60214341D1

    公开(公告)日:2006-10-12

    申请号:DE60214341

    申请日:2002-02-25

    Applicant: IBM

    Abstract: A switching device is able to route the arriving data packets according to data packet destination information to dedicated output ports. The switching arrangement has, for each set of input ports in the switching device, a set of output buffers with an output buffer for storing the payload of each data packet at an address in the output buffer which pertains to the same set of output buffers and belongs to the dedicated output ports. At least one of the output buffers has a set of output queues with an output queue for each output port for storing the address of each payload stored in the corresponding output buffer. An arbiter controls a readout order of the stored addresses. For the output buffers which pertain to the same set of output ports a multiplexer multiplexes according to the readout order the payloads from the output buffers to the output ports.

    4.
    发明专利
    未知

    公开(公告)号:AT338439T

    公开(公告)日:2006-09-15

    申请号:AT02700516

    申请日:2002-02-25

    Applicant: IBM

    Abstract: A switching device is able to route the arriving data packets according to data packet destination information to dedicated output ports. The switching arrangement has, for each set of input ports in the switching device, a set of output buffers with an output buffer for storing the payload of each data packet at an address in the output buffer which pertains to the same set of output buffers and belongs to the dedicated output ports. At least one of the output buffers has a set of output queues with an output queue for each output port for storing the address of each payload stored in the corresponding output buffer. An arbiter controls a readout order of the stored addresses. For the output buffers which pertain to the same set of output ports a multiplexer multiplexes according to the readout order the payloads from the output buffers to the output ports.

    5.
    发明专利
    未知

    公开(公告)号:DE3788649D1

    公开(公告)日:1994-02-10

    申请号:DE3788649

    申请日:1987-10-20

    Applicant: IBM

    Abstract: In a switching system interconnecting transmission links (21-i, 23-i) on which circuit switched (CS) and packet switched (PS) information is transferred, a switch fabric (11) is provided which interconnects a plurality of input ports (15-i) to a plurality of output ports (19-i). The information arriving on incoming links is converted in switch adapters (13-i) to uniform minipackets, each having a routing address designating the required output port. The switch fabric consists of parallel equal switching slices, e.g. binary routing trees (71), which transfer in a non-blocking manner each minipacket from its input port to one output port in response to the routing address. Collecting means (73, 75) are provided at each output port for accepting the minipackets arriving from the different input ports.

    METHOD AND APPARATUS FOR INTERMEDIATE BUFFER SEGMENTATION AND REASSEMBLY

    公开(公告)号:AU2003278452A1

    公开(公告)日:2004-06-18

    申请号:AU2003278452

    申请日:2003-11-05

    Applicant: IBM

    Abstract: The present invention discloses a method and apparatus for transmitting incoming packet data via a data bus to a memory unit and transmitting outgoing packet data from the memory unit to a communication link via the data bus. The method for transmitting packet data via a data bus to a memory unit comprises the steps of receiving a stream of packet data; storing the received packet data in a buffer unit; and in response to the stored packet data, transmitting a burst of packet data to the memory unit, wherein the size of the burst of packet data depends on the properties of the data bus. The method for transmitting outgoing packet data from a memory unit to a communication link via a data bus comprises the steps of transmitting a burst of packet data from the memory unit to a buffer unit, wherein the size of the burst of packet data depends on the properties of the data bus; storing the packet data in the buffer unit; segmenting the packet data in the buffer; and in response to the transmission step, sending the segmented packet data to the communication link.

    High-speed modular switching apparatus for circuit and packet switched traffic

    公开(公告)号:HK7795A

    公开(公告)日:1995-01-27

    申请号:HK7795

    申请日:1995-01-19

    Applicant: IBM

    Abstract: In a switching system interconnecting transmission links (21-i, 23-i) on which circuit switched (CS) and packet switched (PS) information is transferred, a switch fabric (11) is provided which interconnects a plurality of input ports (15-i) to a plurality of output ports (19-i). The information arriving on incoming links is converted in switch adapters (13-i) to uniform minipackets, each having a routing address designating the required output port. The switch fabric consists of parallel equal switching slices, e.g. binary routing trees (71), which transfer in a non-blocking manner each minipacket from its input port to one output port in response to the routing address. Collecting means (73, 75) are provided at each output port for accepting the minipackets arriving from the different input ports.

    8.
    发明专利
    未知

    公开(公告)号:DE3788649T2

    公开(公告)日:1994-06-23

    申请号:DE3788649

    申请日:1987-10-20

    Applicant: IBM

    Abstract: In a switching system interconnecting transmission links (21-i, 23-i) on which circuit switched (CS) and packet switched (PS) information is transferred, a switch fabric (11) is provided which interconnects a plurality of input ports (15-i) to a plurality of output ports (19-i). The information arriving on incoming links is converted in switch adapters (13-i) to uniform minipackets, each having a routing address designating the required output port. The switch fabric consists of parallel equal switching slices, e.g. binary routing trees (71), which transfer in a non-blocking manner each minipacket from its input port to one output port in response to the routing address. Collecting means (73, 75) are provided at each output port for accepting the minipackets arriving from the different input ports.

    9.
    发明专利
    未知

    公开(公告)号:DE60214341T2

    公开(公告)日:2007-09-13

    申请号:DE60214341

    申请日:2002-02-25

    Applicant: IBM

    Abstract: A switching device is able to route the arriving data packets according to data packet destination information to dedicated output ports. The switching arrangement has, for each set of input ports in the switching device, a set of output buffers with an output buffer for storing the payload of each data packet at an address in the output buffer which pertains to the same set of output buffers and belongs to the dedicated output ports. At least one of the output buffers has a set of output queues with an output queue for each output port for storing the address of each payload stored in the corresponding output buffer. An arbiter controls a readout order of the stored addresses. For the output buffers which pertain to the same set of output ports a multiplexer multiplexes according to the readout order the payloads from the output buffers to the output ports.

    High-speed modular switching apparatus for circuit and packet switched traffic

    公开(公告)号:SG173494G

    公开(公告)日:1995-04-28

    申请号:SG173494

    申请日:1994-12-06

    Applicant: IBM

    Abstract: In a switching system interconnecting transmission links (21-i, 23-i) on which circuit switched (CS) and packet switched (PS) information is transferred, a switch fabric (11) is provided which interconnects a plurality of input ports (15-i) to a plurality of output ports (19-i). The information arriving on incoming links is converted in switch adapters (13-i) to uniform minipackets, each having a routing address designating the required output port. The switch fabric consists of parallel equal switching slices, e.g. binary routing trees (71), which transfer in a non-blocking manner each minipacket from its input port to one output port in response to the routing address. Collecting means (73, 75) are provided at each output port for accepting the minipackets arriving from the different input ports.

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