MICROPROGRAM CONTROL SUBSYSTEM
    1.
    发明专利

    公开(公告)号:CA1005922A

    公开(公告)日:1977-02-22

    申请号:CA183583

    申请日:1973-10-17

    Applicant: IBM

    Abstract: A microprogram control subsystem discloses two control stores, one of which is accessed and utilized only on the first cycle of a microprogram sequence utilized to execute an information handling system instruction. A portion of the operation code of the system instruction is used to address the first-cycle control store to provide access to a microinstruction having fewer binary bits than normal microinstructions, and is effective to direct access to the remainder of the microprogram sequence contained in the other control store.

    DATA FLOW MODIFICATION OF INSTRUCTION REGISTER CONTENTS

    公开(公告)号:CA1169573A

    公开(公告)日:1984-06-19

    申请号:CA397732

    申请日:1982-03-05

    Applicant: IBM

    Abstract: The instruction register of a data processing system, which stores a program instruction during at least an initial operation code decoding phase to initiate execution of the instruction, has a number of input gates in addition to the input gates from a program storing main storage device. The additional input gates respond to control or logic signals for gating information from the data flow hardware of the data processing system to the instruction register.

    ERROR DETECTOR FOR AN ASSOCIATIVE DIRECTORY OR TRANSLATOR

    公开(公告)号:CA1072686A

    公开(公告)日:1980-02-26

    申请号:CA258552

    申请日:1976-08-06

    Applicant: IBM

    Inventor: ENGER THOMAS A

    Abstract: ERROR DETECTOR FOR AN ASSOCIATIVE DIRECTORY OR TRANSLATOR Error detection for an associative directory or translator, composed of registers, comparators, and encoder which provides a binary code representation of the location of the register at which a compare occurred, includes a random access register array which responds to the coded location information to read out binary data to be compared with the binary data utilized in the associative compare of the directory or translator.

    4.
    发明专利
    未知

    公开(公告)号:FR2321152A1

    公开(公告)日:1977-03-11

    申请号:FR7620690

    申请日:1976-07-01

    Applicant: IBM

    Inventor: ENGER THOMAS A

    Abstract: Error detection for an associative directory or translator, composed of registers, comparators, and encoder which provides a binary code representation of the location of the register at which a compare occurred, includes a random access register array which responds to the coded location information to read out binary data to be compared with the binary data utilized in the associative compare of the directory or translator.

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