公开(公告)号：CA1176377A

公开(公告)日：1984-10-16

申请号：CA400593

申请日：1982-04-07

Applicant: IBM

Inventor： BULLIONS ROBERT J III ,  CURLEE THOMAS O III ,  GUM PETER H ,  MCGILVRAY BRUCE L ,  RICHARDSON ETHEL L

IPC: G06F9/44 ,  G06F9/455 ,  G06F9/46 ,  G06F12/10 ,  G11C9/00

Abstract: PO9-80-005 The described embodiment provides translation look-aside buffer (TLB) hardware in a CP that receives the results of double-level address translations to eliminate the need for having shadow tables for the second-level in a virtual machine (VM) environment. Each TLB entry contains hardware which indicates whether the address sent by the CP Instruction Execution (IE) unit for translation is a guest or host/native request, and for a guest request if it is a real or virtual address. Intermediate translations for a double-level translation are inhibited from being loaded into the TLB. Guest entries are purged from the TLB without disturbing any host entries. An accelerated preferred guest mode in the CP forces its hardware adder translation hard ware to translate each accelerated preferred guest request, since it requires only a single level translation. A nonaccelerated guest request is instead translated by microcode. A limit check register is provided to check preferred guest addresses without causing performance degradation.

公开(公告)号：CA2060555A1

公开(公告)日：1992-10-25

申请号：CA2060555

申请日：1992-02-03

Applicant: IBM

Inventor： BULLIONS ROBERT J III ,  HILL RONALD F ,  NADAS STEPHEN J ,  PEDERSEN RAYMOND J

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/318 ,  G06F9/46 ,  G06F15/16

Abstract: P09-91-013 SYSTEM AND METHOD FOR DRAINING AN INSTRUCTION PIPELINE The present invention comprises a system and method for selectively draining an instruction pipeline. In one embodiment, the invention is implemented in the context of pipelined processor having an interpretive storage and multiple execution units. In the described system, the instructions held in the interpretive storage are referred to as "milli-instructions" and the interpretive execution mode is referred to as "milli-mode". Additional hardware controlled instructions (private milli-mode only instructions) are added to provide control functions or to improve performance. These private milli-mode instructions augment the architected instruction set. Milli-mode routines can intermingle the milli-mode only instructions with architected instructions to implement complex functions. In order to provide an enhanced level of flexibility and efficiency, the above-described embodiment includes a milli-instruction that causes the pipeline to drain. This milli-instruction, called DRAIN INSTRUCTION PIPELINE (DIP) allows greater selectivity by the coder over (1) when to drain the pipeline and (2) what type of pipeline drain to perform. In the preferred embodiment, the DIP instruction enables the coder to cause the system to suspend decoding until a selected event occurs. Specifically, the instruction includes options to suspend decoding until a selected one of the following events has occurred: all conceptually previous macro instructions have completed; all conceptually previous milli-code instructions have completed; all conceptually previous instructions have completed; all store requests have reached the point where no exceptions will occur, but the actual store may not have completed; all conceptually previous stores from all conceptually previous units-of-operation have completed (serialize); or invalidate instruction buffers and fetch the next sequential macro-instructions.

公开(公告)号：CA1169573A

公开(公告)日：1984-06-19

申请号：CA397732

申请日：1982-03-05

Applicant: IBM

Inventor： BULLIONS ROBERT J III ,  ENGER THOMAS A

IPC: G06F9/30 ,  G06F9/318 ,  G11C9/00

Abstract: The instruction register of a data processing system, which stores a program instruction during at least an initial operation code decoding phase to initiate execution of the instruction, has a number of input gates in addition to the input gates from a program storing main storage device. The additional input gates respond to control or logic signals for gating information from the data flow hardware of the data processing system to the instruction register.