公开(公告)号：DE2346565A1

公开(公告)日：1974-05-02

申请号：DE2346565

申请日：1973-09-15

Applicant: IBM

Inventor： CASS EUGENE EDWARD ,  ENICHEN WILLIAM ALBERT ,  HAVAS JANOS

IPC: H05K3/46 ,  H01L21/306 ,  H01L21/768 ,  H01L23/522 ,  C23C13/00 ,  H01L1/14

Abstract: In this method, the multi-level interconnection metallurgy system is made more compact by eliminating the need for pads normally associated with via connections between the metallurgy layers. The method consists of forming a first dielectric layer on a semiconductor substrate, forming the first interconnection metallurgy level on the first layer, depositing a second dielectric layer over the metallurgy layer wherein the second dielectric layer is a material different from the material of the first dielectric layer, forming via holes in the second dielectric layer of a diameter substantially equal to or larger than the width of the underlying interconnection lines of the first metallurgy pattern, and forming a second interconnection metallurgy system over the second dielectric layer with the conductive lines of the second metallurgy layer having a uniform width over the via holes.