公开(公告)号：US3873361A

公开(公告)日：1975-03-25

申请号：US42003473

申请日：1973-11-29

Applicant: IBM

Inventor： FRANCO JACK R ,  HAVAS JANOS ,  LEVINE HAROLD A

IPC: G03F1/00 ,  C23C14/04 ,  G03F1/08 ,  G03F7/09 ,  H01L21/00 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/312 ,  H01L23/29 ,  H05K3/02 ,  H05K3/04 ,  B44D1/18 ,  H05K1/00

CPC classification number: H05K3/048 ,  C23C14/042 ,  G03F7/094 ,  H01L21/00 ,  H01L21/312 ,  H01L23/29 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for use in depositing thin films in the fabrication of integrated circuits which avoids edge tearing of the films. The method involves depositing a non-photosensitive organic polymeric material on a substrate, and forming on said polymeric layer a masking layer of an inorganic material, preferably metal, having openings in a selected pattern. Then, forming, by reactive sputter etching, utilizing the metallic mask as a barrier, openings through the polymeric layer extending to the substrate, the openings in the polymeric layer being aligned with and laterally wider than the corresponding openings in the metallic masking layer. The thin film to be deposited is then applied over the structure; it is, thereby, deposited on the substrate in said openings. Then, the remaining polymeric layer is removed, lifting off the masking layer and the thin film above the polymeric layer to leave thin film deposited in a selected pattern in the openings.

Abstract translation: 一种用于在制造集成电路中沉积薄膜的方法，其避免了膜的边缘撕裂。 该方法包括将非感光有机聚合物材料沉积在基底上，并在所述聚合物层上形成具有选定图案开口的无机材料（优选金属）的掩蔽层。 然后，通过反应性溅射蚀刻，利用金属掩模作为屏障，通过聚合物层的开口延伸到基底，聚合物层中的开口与金属掩蔽层中相应的开口对准并且横向宽于金属掩模层中的相应开口。 然后将待沉积的薄膜施加在结构上; 从而沉积在所述开口中的基板上。 然后，除去剩余的聚合物层，从掩模层和聚合物层上方的薄膜上取下薄膜，以在开口中以选定的图案沉积薄膜。

公开(公告)号：US3664942A

公开(公告)日：1972-05-23

申请号：US3664942D

申请日：1970-12-31

Applicant: IBM

Inventor： HAVAS JANOS ,  LECHATON JOHN S

IPC: C23F4/00 ,  H01J37/32 ,  C23C15/00

CPC classification number: H01J37/32935 ,  C23F4/00

Abstract: The end point in sputter-etching metal layers, for example, from substrates is determined by employing a silicon, quartz, or the like, monitor control wafer in the sputter-etching environment which wafer has been previously coated with said metal, for example, in the same run as that used to fabricate the workpiece substrate. Thus, the monitor control wafer exhibits the same thickness of metal, or the like, as the thickness of the metal layer to be selectively sputter-etched from the substrate. The temperature exhibited by the monitor control wafer during the sputter-etching material removal process in monitored by an infrared radiation thermometer, by way of a quartz window. When the layer of metal, or the like, has been removed from the monitor control wafer, the temperature, as sensed by the infrared radiation thermometer during sputter-etching, declines thereby indicating the end point in the removal process of the metal layer, or the like.

Abstract translation: 例如通过采用硅，石英等在溅射蚀刻金属层中的溅射蚀刻金属层中的终点，通过采用硅，石英等来监测晶片已经预先用所述金属涂覆的溅射蚀刻环境中的控制晶片， 与用于制造工件基板的操作相同。 因此，作为要从基板选择性地溅射蚀刻的金属层的厚度，监视器控制晶片呈现相同厚度的金属等。 在溅射蚀刻材料去除过程期间由监测控制晶片呈现的温度由红外辐射温度计通过石英窗监测。 当已经从监视器控制晶片去除了金属层等时，在溅射蚀刻期间由红外辐射温度计感测到的温度下降，从而表明金属层的去除过程中的终点，或 类似。

公开(公告)号：FR2310633A1

公开(公告)日：1976-12-03

申请号：FR7608563

申请日：1976-03-12

Applicant: IBM

Inventor： FRANCO JACK R ,  HAVAS JANOS ,  ROMPALA LEWIS J

IPC: H01L21/302 ,  C23C14/04 ,  C23F4/00 ,  G03F7/09 ,  G03F7/095 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/312 ,  H01L21/3205 ,  H05K3/02 ,  H05K3/04 ,  H01L21/72

Abstract: A lift-off method for use in depositing thin films in the fabrication of integrated circuits which avoids edge tearing of the films. The method involves depositing an organic polymeric first masking material on a substrate, and forming on said material a layer of a polydimethylsiloxane resin material. The material, in turn, is covered by a second masking layer, preferably an organic polymeric resist material into which openings are placed in a selected pattern utilizing lithographic techniques. Then, conforming openings are placed in the underlying polydimethylsiloxane resin material and the openings are extended through the underlying resist material by successive reactive sputter etching steps to expose the substrate surface in the aforesaid selected pattern. The thin film to be deposited is then applied over the resulting structure; it is, thereby, deposited on the substrate in said openings. The final reactive sputter etching step affords edges in the openings through the resin material layer which overhang the edges in the openings through the first masking layer affording easy lift-off of the unwanted areas of the deposited film when the first masking layer is totally removed by application of solvent.

公开(公告)号：DE2448535A1

公开(公告)日：1975-06-05

申请号：DE2448535

申请日：1974-10-11

Applicant: IBM

Inventor： FRANCO JACK RICHARD ,  HAVAS JANOS ,  LEVINE HAROLD A

IPC: G03F1/00 ,  C23C14/04 ,  G03F1/08 ,  G03F7/09 ,  H01L21/00 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/312 ,  H01L23/29 ,  H05K3/02 ,  H05K3/04 ,  H05K3/16

Abstract: A method for use in depositing thin films in the fabrication of integrated circuits which avoids edge tearing of the films. The method involves depositing a non-photosensitive organic polymeric material on a substrate, and forming on said polymeric layer a masking layer of an inorganic material, preferably metal, having openings in a selected pattern. Then, forming, by reactive sputter etching, utilizing the metallic mask as a barrier, openings through the polymeric layer extending to the substrate, the openings in the polymeric layer being aligned with and laterally wider than the corresponding openings in the metallic masking layer. The thin film to be deposited is then applied over the structure; it is, thereby, deposited on the substrate in said openings. Then, the remaining polymeric layer is removed, lifting off the masking layer and the thin film above the polymeric layer to leave thin film deposited in a selected pattern in the openings.

公开(公告)号：DE2967291D1

公开(公告)日：1984-12-13

申请号：DE2967291

申请日：1979-11-27

Applicant: IBM

Inventor： HAVAS JANOS ,  PAAL GABOR

IPC: H01L21/3205 ,  H01L21/027 ,  H01L21/28 ,  H01L21/306 ,  H01L21/00

Abstract: A method for depositing thin film patterns of very small and controllable dimensions in the fabrication of integrated circuits which avoids edge tearing of the films. A non-photosensitive organic polymeric first masking layer is deposited on the integrated circuit substrate. Upon this layer is deposited a layer of silicon nitride using plasma deposition techniques employing a gaseous source. The silicon nitride layer is covered by a second masking layer, preferably an organic polymeric resist material, through which apertures are formed in preselected patterns using standard lithographic masking and etching techniques. The silicon nitride layer is then reactive ion etched with CF4 through the apertures formed in the second masking layer. The first masking layer is then etched through the apertures in the second masking layer and silicon nitride layer using reactive ion etching techniques. The etching of the first masking layer continues until the first masking layer is undercut beyond the edges of the aperture in the silicon nitride layer so that the silicon nitride layer forms an overhang of the aperture in the first masking layer. The thin film to be deposited is then applied over the resulting structure including the surface of the silicon nitride layer and the substrate exposed through the apertures. Because of the overhang, a discontinuity is formed between the thin film deposited upon the exposed surface of the substrate and that formed upon the outer surface of the silicon nitride layer so that when the first masking layer is dissolved, the film deposited upon the substrate is left without any edge tearing between it and the removed portions of the film.

公开(公告)号：CA1032396A

公开(公告)日：1978-06-06

申请号：CA211474

申请日：1974-10-16

Applicant: IBM

Inventor： FRANCO JACK R ,  HAVAS JANOS ,  LEVINE HAROLD A

IPC: G03F1/00 ,  C23C14/04 ,  G03F1/08 ,  G03F7/09 ,  H01L21/00 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/312 ,  H01L23/29 ,  H05K3/02 ,  H05K3/04 ,  H01L

Abstract: A method for use in depositing thin films in the fabrication of integrated circuits which avoids edge tearing of the films. The method involves depositing a non-photosensitive organic polymeric material on a substrate, and forming on said polymeric layer a masking layer of an inorganic material, preferably metal, having openings in a selected pattern. Then, forming, by reactive sputter etching, utilizing the metallic mask as a barrier, openings through the polymeric layer extending to the substrate, the openings in the polymeric layer being aligned with and laterally wider than the corresponding openings in the metallic masking layer. The thin film to be deposited is then applied over the structure; it is, thereby, deposited on the substrate in said openings. Then, the remaining polymeric layer is removed, lifting off the masking layer and the thin film above the polymeric layer to leave thin film deposited in a selected pattern in the openings.

公开(公告)号：DE2617914A1

公开(公告)日：1976-11-18

申请号：DE2617914

申请日：1976-04-23

Applicant: IBM

Inventor： FRANCO JACK RICHARD ,  HAVAS JANOS ,  ROMPALA LEWIS JOSEPH

IPC: H01L21/302 ,  C23C14/04 ,  C23F4/00 ,  G03F7/09 ,  G03F7/095 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/312 ,  H01L21/3205 ,  H05K3/02 ,  H05K3/04 ,  H05K3/08 ,  C23C15/00

Abstract: A lift-off method for use in depositing thin films in the fabrication of integrated circuits which avoids edge tearing of the films. The method involves depositing an organic polymeric first masking material on a substrate, and forming on said material a layer of a polydimethylsiloxane resin material. The material, in turn, is covered by a second masking layer, preferably an organic polymeric resist material into which openings are placed in a selected pattern utilizing lithographic techniques. Then, conforming openings are placed in the underlying polydimethylsiloxane resin material and the openings are extended through the underlying resist material by successive reactive sputter etching steps to expose the substrate surface in the aforesaid selected pattern. The thin film to be deposited is then applied over the resulting structure; it is, thereby, deposited on the substrate in said openings. The final reactive sputter etching step affords edges in the openings through the resin material layer which overhang the edges in the openings through the first masking layer affording easy lift-off of the unwanted areas of the deposited film when the first masking layer is totally removed by application of solvent.

公开(公告)号：DE2346565A1

公开(公告)日：1974-05-02

申请号：DE2346565

申请日：1973-09-15

Applicant: IBM

Inventor： CASS EUGENE EDWARD ,  ENICHEN WILLIAM ALBERT ,  HAVAS JANOS

IPC: H05K3/46 ,  H01L21/306 ,  H01L21/768 ,  H01L23/522 ,  C23C13/00 ,  H01L1/14

Abstract: In this method, the multi-level interconnection metallurgy system is made more compact by eliminating the need for pads normally associated with via connections between the metallurgy layers. The method consists of forming a first dielectric layer on a semiconductor substrate, forming the first interconnection metallurgy level on the first layer, depositing a second dielectric layer over the metallurgy layer wherein the second dielectric layer is a material different from the material of the first dielectric layer, forming via holes in the second dielectric layer of a diameter substantially equal to or larger than the width of the underlying interconnection lines of the first metallurgy pattern, and forming a second interconnection metallurgy system over the second dielectric layer with the conductive lines of the second metallurgy layer having a uniform width over the via holes.

公开(公告)号：DE69029586T2

公开(公告)日：1997-07-17

申请号：DE69029586

申请日：1990-10-15

Applicant: IBM

Inventor： DEAN ALICIA ,  FITZSIMMONS JOHN ,  HAVAS JANOS ,  MCCORMICK BARRY ,  SHAH PROBODH

IPC: G03F7/42 ,  H01L21/027 ,  H01L21/30

公开(公告)号：CA1089112A

公开(公告)日：1980-11-04

申请号：CA180181

申请日：1973-09-04

Applicant: IBM

Inventor： CASS EUGENE E ,  ENICHEN WILLIAM A ,  HAVAS JANOS

IPC: H05K3/46 ,  H01L21/306 ,  H01L21/768 ,  H01L23/522 ,  H05K1/04

Abstract: METHOD OF FORMING A COMPACT MULTI-LEVEL INTERCONNECTION METALLURGY SYSTEM FOR SEMICONDUCTOR DEVICES In this method, the multi-level interconnection metallurgy system is made more compact by eliminating the need for pads normally associated with via connections between the metallurgy layers. The method consists of forming a first dielectric layer on a semiconductor substrate, forming the first interconnection metallurgy level on the first layer, depositing a second dielectric layer over the metallurgy layer wherein the second dielectric layer is a material different from the material of the first dielectric layer, forming via holes in the second dielectric layer of a diameter substantially equal to or larger than the width of the underlying interconnection lines of the first metallurgy pattern, and forming a second interconnection metallurgy system over the second dielectric layer with the conductive lines of the second metallurgy layer having a uniform width over the via holes.