公开(公告)号：JPH11176152A

公开(公告)日：1999-07-02

申请号：JP27813098

申请日：1998-09-30

Applicant: IBM

Inventor： MICHAEL P CLINTON ,  MARK R FOSHEEL ,  ERIC L HEADBERG ,  KELLOGG MARK W ,  WILBER D PRICER

IPC: G11C11/41 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409

Abstract: PROBLEM TO BE SOLVED: To reduce wait time between initial page hits by dividing the logic bank of a memory element into two segments and optimizing an array. SOLUTION: Logic banks A-D are divided into two segments 50-51, 52-53, 54-55, and 56-57, where the two segments 51, 53, 55, and 57 include a high-speed random access memory (FRAM). The first or initial 8-bit data from each group consisting of 8 bytes are transferred from high-speed FRAMs 51, 53, 55, and 57 to a high-speed read register 61 and to an I/O pin of elements via an immediate multiplexer 76 during reading access for the initial access of a selection page. While the initial data are being read, succeeding access from the low-speed DRAMs 50, 52, 54, and 56 is initiated and an I/O pin 78 is being strobed continuously by a system clock after the initial data, thus improving wait time.