公开(公告)号：JP2000339216A

公开(公告)日：2000-12-08

申请号：JP2000124596

申请日：2000-04-25

Applicant: IBM

Inventor： DELL TIMOTHY J ,  HAZELZET BRUCE G ,  KELLOGG MARK W ,  MILLER CHRISTOPHER P

IPC: G06F1/32 ,  G06F12/02 ,  G06F12/06 ,  G11C11/403

Abstract: PROBLEM TO BE SOLVED: To provide an improved memory module with a signal processing element, preferably a DSP, at least one bank of a memory chip, preferably first and second banks to be individually addressed and its use in a computer system. SOLUTION: The memory module 8 is provided with first and second banks 12, 13 to be respectively addressed of the DSP of the memory chip. The first bank is constituted so as to basically function under control of the signal processing element 36, the second bank is constituted so as to basically function under control of a system memory controller 28, however, all parts of respective memory banks are addressed by both of the signal processing element and the system memory controller. Both banks of the memory chip is placed on at least one high power state and at least one low power state by either of the system memory controller or the DSP.

公开(公告)号：JPH11149772A

公开(公告)日：1999-06-02

申请号：JP23402398

申请日：1998-08-20

Applicant: IBM

Inventor： DELL TIMOTHY JAY ,  FENG GEORGE C ,  KELLOGG MARK W

IPC: G11C11/407 ,  G06F12/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  H05K1/02 ,  H05K1/14

Abstract: PROBLEM TO BE SOLVED: To provide a synchronous dynamic random access memory which has two banks of connectors which accommodate single or dual in-line memory modules. SOLUTION: A clock 28 is provided near connectors 12-26 and generates a clock signal with a known rising time. Clock wirings 30 are provided between the clock and the connectors and module wirings transmit clock pulses from the connectors to a memory. The lengths and impedances of the wirings are so selected as to have the round-trip delay time of the clock pulse between the clock and the memory smaller than the known rise time of the clock pulse. It is recommended that the clock is provided between two banks of connectors to minimize the wiring lengths and reduce coupling noises.

公开(公告)号：JP2004310751A

公开(公告)日：2004-11-04

申请号：JP2004066400

申请日：2004-03-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ELLIS WAYNE F ,  KELLOGG MARK W ,  PHIPPS DANIEL J

IPC: G06F12/16 ,  G06F11/10 ,  G06F12/02 ,  G11C7/10 ,  G11C7/22 ,  G11C11/40 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4093

CPC classification number: G11C7/109 ,  G06F11/1016 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4093 ,  G11C2207/104

Abstract: PROBLEM TO BE SOLVED: To provide a method for performing a command cancel (CC) function on a dynamic random access memory (DRAM) semiconductor device for enhancing reliability and speed of a memory system. SOLUTION: The CC function takes advantage of the intrinsic delays associated with memory read operations at high clock frequencies, and the increased write latency commensurate with increased read latencies where non-zero latencies for and write operations are the norm by permitting address and command ECC structures to operate in parallel with the address and command re-drive circuits. The CC function is extendable to future DDR2 and DDR3 operating requirements in which latency of higher frequency modes will increase due to the shift from 2 bit pre-fetch to 4 and 8 bit pre-fetch architecture. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JPH11176152A

公开(公告)日：1999-07-02

申请号：JP27813098

申请日：1998-09-30

Applicant: IBM

Inventor： MICHAEL P CLINTON ,  MARK R FOSHEEL ,  ERIC L HEADBERG ,  KELLOGG MARK W ,  WILBER D PRICER

IPC: G11C11/41 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409

Abstract: PROBLEM TO BE SOLVED: To reduce wait time between initial page hits by dividing the logic bank of a memory element into two segments and optimizing an array. SOLUTION: Logic banks A-D are divided into two segments 50-51, 52-53, 54-55, and 56-57, where the two segments 51, 53, 55, and 57 include a high-speed random access memory (FRAM). The first or initial 8-bit data from each group consisting of 8 bytes are transferred from high-speed FRAMs 51, 53, 55, and 57 to a high-speed read register 61 and to an I/O pin of elements via an immediate multiplexer 76 during reading access for the initial access of a selection page. While the initial data are being read, succeeding access from the low-speed DRAMs 50, 52, 54, and 56 is initiated and an I/O pin 78 is being strobed continuously by a system clock after the initial data, thus improving wait time.

公开(公告)号：CA2130408A1

公开(公告)日：1995-05-18

申请号：CA2130408

申请日：1994-08-18

Applicant: IBM

Inventor： FUOCO DANIEL P ,  HERRING CHRISTOPHER M ,  KELLOGG MARK W ,  LENTO JORGE E

IPC: G06F11/10 ,  G06F11/20

Abstract: A computer system and method of using the same is provided which system has a CPU, a bus, and add-on memory. The CPU has parity generation and detection capabilities but does not necessarily have error correction capabilities. The present invention provides error correction capabilities in add-on memory or in association with the add-on memory which allows error correction of single bit read errors from the add-on memory and also allows for the detection of multiple bit read errors and the detection of write errors by byte location of the write errors.

公开(公告)号：DE69924179D1

公开(公告)日：2005-04-21

申请号：DE69924179

申请日：1999-04-29

Applicant: IBM

Inventor： DELL TIMOTHY J ,  HEDBERG ERIK L ,  KELLOGG MARK W

IPC: G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C7/00

Abstract: A memory device is provided which stacks commands and internally executes each command at the appropriate time, thereby ensuring contiguous data I/O. The memory device is capable of initiating memory accesses either immediately or "stacking" the command along with a "clock count". The clock count defines the number of clock cycles that must occur prior to execution of the command by the memory device. The memory device initiates memory accesses either immediately, or delayed by the number of clocks defined by the clock count for that command. The memory device operates as a slave to the memory controller and therefore has no ability to execute instructions at a time other than that defined by the memory controller.

公开(公告)号：DE69924179T2

公开(公告)日：2006-03-23

申请号：DE69924179

申请日：1999-04-29

Applicant: IBM

Inventor： DELL TIMOTHY J ,  HEDBERG ERIK L ,  KELLOGG MARK W

IPC: G11C7/00 ,  G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401

Abstract: A memory device is provided which stacks commands and internally executes each command at the appropriate time, thereby ensuring contiguous data I/O. The memory device is capable of initiating memory accesses either immediately or "stacking" the command along with a "clock count". The clock count defines the number of clock cycles that must occur prior to execution of the command by the memory device. The memory device initiates memory accesses either immediately, or delayed by the number of clocks defined by the clock count for that command. The memory device operates as a slave to the memory controller and therefore has no ability to execute instructions at a time other than that defined by the memory controller.

公开(公告)号：CA2130406A1

公开(公告)日：1995-05-18

申请号：CA2130406

申请日：1994-08-18

Applicant: IBM

Inventor： FUOCO DANIEL P ,  HERRING CHRISTOPHER M ,  KELLOGG MARK W ,  LENTO JORGE E

IPC: G06F12/16 ,  G06F11/10 ,  G06F11/20

Abstract: ERROR CORRECTION CODE ON ADD-ON CARDS FOR WRITING PORTIONS OF DATA WORDS The present invention provides a computer system and method of using the same. Add-on memory cards for the system are provided which cards have error correction code logic on the card, and logic to do partial writes of data words. The system has a central processing unit (CPU), a BUS interconnecting the CPU and the add-on memory cards. The CPU or associated components are configured to write data and read data from the add-on memory as several data bytes constituting data words. The system is further configured either within the CPU or as a separate function to generate parity bits associated with each of the bytes of data the CPU writes to the add-on memory and to read parity bits associated with data the CPU reads from the add-on memory and regenerate new parity bits and compare the newly generated parity bits with the original parity bits to detect data errors on data read from the add-on memory. The system itself does not contain error correction code (ECC). The add-on memory has ECC logic to identify any byte having a single bit error in the data bytes or the parity bits written by the CPU to the add-on memory and to correct all single bit errors in data read from the add-on memory to the CPU. The error correcting code includes logic to generate parity bits in the data bytes written by the CPU to the addon memory and logic to compare the parity bits written by the CPU with those generated by the error correcting code logic.

公开(公告)号：CA2130405A1

公开(公告)日：1995-05-18

申请号：CA2130405

申请日：1994-08-18

Applicant: IBM

Inventor： FUOCO DANIEL P ,  HERRING CHRISTOPHER M ,  KELLOGG MARK W ,  LENTO JORGE E

IPC: G06F11/10 ,  G06F11/20

Abstract: The present invention provides a computer system and method of using the same. Add-on memory cards for the system are provided which cards have error correction code logic on the card, and logic to do partial writes of data words. The system has a central processing unit (CPU), a BUS interconnecting the CPU and the add-on memory cards. The CPU or associated components are configured to write data and read data from the add-on memory as several data bytes constituting data words. The system is further configured either within the CPU or as a separate function to generate parity bits associated with each of the bytes of data the CPU writes to the add-on memory and to read parity bits associated with data the CPU reads from the add-on memory and regenerate new parity bits and compare the newly generated parity bits with the original parity bits to detect data errors on data read from the add-on memory. The system itself does not contain error correction code (ECC). The add-on memory has ECC logic to identify any byte having a single bit error in the data bytes or the parity bits written by the CPU to the add-on memory and to correct all single bit errors in data read from the add-on memory to the CPU. The error correcting code includes logic to generate parity bits in the data bytes written by the CPU to the add-on memory and logic to compare the parity bits written by the CPU with those generated by the error correcting code logic. Also provided is a circuitry card technique to block or by-pass error reporting and correcting during initialization.