公开(公告)号：DE3275691D1

公开(公告)日：1987-04-16

申请号：DE3275691

申请日：1982-12-14

Applicant: IBM

Inventor： ESTEBAN DANIEL JACQUES ,  JONES GARDNER DULANY ,  ROGERS LEE SHANNON

IPC: H04M11/06 ,  H03M7/30 ,  H04B1/66 ,  H04B14/04 ,  H04J1/00 ,  H04J3/00 ,  H04J3/04 ,  H04J3/16 ,  H04J3/17 ,  H04J4/00 ,  H04J3/24

Abstract: A statistical multiplexer employing split band encoding in which each port has associated with it a sub-bank of filters (110F-130F) and a sub-bank of quantizers (110Q-130Q). The common equipment assigns the coding resource across all the ports rather than only within a single port. This equipment includes a power level measurement device (170) which is separately responsive to the output of each of the filters and provides an input to a signalling control and multiplexing equipment (180) and to a bit allocation device (171) which provides a control signal to each of the quantizers providing to each of them a bit allocation out of the pool of bit capacity for the entire multiplexer.

公开(公告)号：DE2860220D1

公开(公告)日：1981-01-22

申请号：DE2860220

申请日：1978-12-08

Applicant: IBM

Inventor： ESTEBAN DANIEL JACQUES ,  GALAND CLAUDE ROBERT ,  MAUDUIT DANIEL ,  MENEZ JEAN

IPC: H03M7/30 ,  H04B1/66 ,  H04B14/04 ,  G10L1/08

Abstract: A voice signal is transmitted digitally at reduced bit rate by use of data compression. The original frequency components of a telephone band width of the voice signal sampled at 8 KHz and quantized with 12 bits are transformed into three parameters: SIGNAL data representing adaptive quantization for lower frequency (300-800 Hz) sub-bands; COEF data representing pre-emphasized parcor type coefficients for the higher frequency (800-3000 Hz) band; and, ENERGY data representing higher frequency short term energy level. The three parameters are multiplexed for transmission in binary-code form, thereby representing a recoding of the original binary-coded voice signals.

公开(公告)号：GB1256249A

公开(公告)日：1971-12-08

申请号：GB5968868

申请日：1968-12-16

Applicant: IBM

Inventor： ESTEBAN DANIEL JACQUES

IPC: H03F1/08 ,  H03F1/56 ,  H03F3/30 ,  H03F3/45 ,  H03F3/50

Abstract: 1,256,249. Transistor amplifying circuits. INTERNATIONAL BUSINESS MACHINES CORP. 16 Dec., 1968 [15 Dec., 1967], No. 59688/68. Heading H3T. An operational amplifier comprises sequentially a differential amplifier first stage having a transistor arranged as a current inverter in an output thereof, a low-input and high-output impedance transformer second stage coupled to the output of the first stage and a high-input and low-output impedance third stage coupled to the output of the second stage. The invention is derived from an arrangement in which the differential stage comprises transistors T1, T2, Fig. 6, with a common emitter resistor R1, the second stage transistor T3 of opposite conductivity type in common base connection with its collector load comprising the collector to emitter path of transistor T4, and the third stage a fieldeffect transistor T5 connected as a sourcefollower. In an embodiment, the first stage may comprise any one of the arrangements A1-A3, Fig. 7, the second stage any one of the arrangements B1-B3 and the third stage any of the arrangements C1-C3. In each of the arrangements A1-A3 the base of the current inverter transistor T0 is coupled to the collector of transistor T1; in arrangement A1 its collector is connected together with the collector of transistor T2 to the stage output terminal a. In arrangement A2 its collector comprises the stage output terminal a, its emitter being also driven from the collector of transistor T2, while in arrangement A3 the stage output terminal a is connected to the collector of transistor T2, while the collector of transistor T0 is connected to an additional stage output terminal b. In arrangement B1 the grounded-base transistor with input terminal a 1 has the emitter-collector path of a further transistor T4 as its collector load; an additional input terminal b 1 , at the emitter of transistor T4, is provided for the arrangement of A3. In the arrangement B2 an additional transistor T4 1 is placed in series with the transistor T4; this also occurs in the arrangement B3 but in this a further transistor T3 1 is additionally placed in series with transistor T3. The arrangement C1 comprises a pair of emitter-followers T6, T7 in cascade, while in the arrangement C2 each of these transistors has a further transistor T8, T9 respectively as its emitter load. In the arrangement C3, a first emitter-follower T6 has a further transistor T8 as its emitter load, and it drives a complementary-pair emitter follower output stage comprising transistors T7, T10.