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    2.
    发明专利
    未知

    公开(公告)号：FR2811788B1

    公开(公告)日：2003-10-31

    申请号：FR0105483

    申请日：2001-04-24

    Applicant: IBM CORP INTERNAT BUSINESS MAC

    Inventor： BAUCHOT FREDERIC ,  MAUDUIT DANIEL ,  HARARI ALBERT

    IPC: G06F17/24 ,  G06F17/30 ,  G06F19/00

    Abstract: The present invention relates to the field of information processing by digital computers, and more particularly to a method and system, in an electronic spreadsheet, of applying one or a plurality of user-defined options within one or a plurality of cells. The method comprises the steps of: defining for each option a boolean variable with a first value and a second value, preferably a "true" or "false" value; for each of said one or plurality of cells: referencing one or a plurality of boolean variables; associating a logical or mathematical operation with each boolean variable; for each of said one or plurality of referenced boolean variables in each of said one or plurality of cells: specifying a default value, said default value being defined as the value of the cell when the referenced boolean variable is set to the first value, preferably when the boolean variable is set to the "false" value; specifying a delta value by applying to the specified cell default value, the operation associated with the referenced boolean variable when the boolean variable is set to the second value, preferably when the boolean variable is set to the "true" value; setting each boolean variable to the first value or to the second value; for each of said one or plurality of cells: computing said one or plurality of delta values.

    4.
    发明专利
    未知

    公开(公告)号：AT144870T

    公开(公告)日：1996-11-15

    申请号：AT93480087

    申请日：1993-06-30

    Applicant: IBM

    Inventor： GALAND CLAUDE ,  MAUDUIT DANIEL ,  PAUPORTE ANDRE ,  SPAGNOL VICTOR ,  LEBIZAY GERALD ,  MUNIER JEAN-MARIE ,  SAINT-GEORGES ERIC

    IPC: H04L29/06

    Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.

    Programmable High Performance Data Communication Adapter for High Speed Paquet Transmission Networks
    5.
    发明专利
    Programmable High Performance Data Communication Adapter for High Speed Paquet Transmission Networks 未知

    公开(公告)号：CA2120558A1

    公开(公告)日：1994-12-31

    申请号：CA2120558

    申请日：1994-04-05

    Applicant: IBM

    Inventor： GALAND CLAUDE ,  LEBIZAY GERALD ,  MAUDUIT DANIEL ,  MUNIER JEAN-MARIE ,  PAUPORTE ANDRE ,  SAINT-GEORGES ERIC ,  SPAGNOL VICTOR

    IPC: H04L29/06 ,  H04L12/56

    Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.

    METHOD AND SYSTEM FOR SPEECH DATA COMPRESSION
    6.
    发明专利
    METHOD AND SYSTEM FOR SPEECH DATA COMPRESSION 未知

    公开(公告)号：DE2860220D1

    公开(公告)日：1981-01-22

    申请号：DE2860220

    申请日：1978-12-08

    Applicant: IBM

    Inventor： ESTEBAN DANIEL JACQUES ,  GALAND CLAUDE ROBERT ,  MAUDUIT DANIEL ,  MENEZ JEAN

    IPC: H03M7/30 ,  H04B1/66 ,  H04B14/04 ,  G10L1/08

    Abstract: A voice signal is transmitted digitally at reduced bit rate by use of data compression. The original frequency components of a telephone band width of the voice signal sampled at 8 KHz and quantized with 12 bits are transformed into three parameters: SIGNAL data representing adaptive quantization for lower frequency (300-800 Hz) sub-bands; COEF data representing pre-emphasized parcor type coefficients for the higher frequency (800-3000 Hz) band; and, ENERGY data representing higher frequency short term energy level. The three parameters are multiplexed for transmission in binary-code form, thereby representing a recoding of the original binary-coded voice signals.

    8.
    发明专利
    未知

    公开(公告)号：DE3881883T2

    公开(公告)日：1993-12-23

    申请号：DE3881883

    申请日：1988-08-30

    Applicant: IBM

    Inventor： CUKIER MAURICE ,  MAUDUIT DANIEL ,  ORENGO GERARD

    IPC: H03M3/04 ,  H03H17/00 ,  H03H17/06 ,  H04L7/033

    Abstract: Digital filter used in a sigma-delta decoder wherein each input sample is involved in the computation of three consecutive PCM output samples. During one sigma-delta sampling period, the filter performs three parallel operations by multiplexing (44) one adder (36) running three times faster than the sigma-delta clock for loading one of three accumulators (38, 40, 42). As the analog-to-digital converter must be kept in phase with remote modem transmit clock, the PCM sampling clock is controlled by the phase tracking performed by adding or subtracting one period of the crystal oscillator from time to time to the PCM sampling clock period. Rotating the order the accumulators are loaded by the adder each PCM sampling time enables to have zero as last coefficient value to add to the accumulator the contents of which is used as PCM output samples. Thus, each PCM sample value is available in the corresponding accumulator one sigma-delta clock period before the last computation. In case of a correction which shortens or lengthens the PCM sampling period, this correction does not change the PCM sample value to be output since the last computation which is either cancelled or repeated, consists in adding zero to the previous accumulator contents.

    9.
    发明专利
    未知

    公开(公告)号：DE69305734T2

    公开(公告)日：1997-05-15

    申请号：DE69305734

    申请日：1993-06-30

    Applicant: IBM

    Inventor： GALAND CLAUDE ,  MAUDUIT DANIEL ,  PAUPORTE ANDRE ,  SPAGNOL VICTOR ,  LEBIZAY GERALD ,  MUNIER JEAN-MARIE ,  SAINT-GEORGES ERIC

    IPC: H04L29/06

    Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.

    10.
    发明专利
    未知

    公开(公告)号：DE69305734D1

    公开(公告)日：1996-12-05

    申请号：DE69305734

    申请日：1993-06-30

    Applicant: IBM

    Inventor： GALAND CLAUDE ,  MAUDUIT DANIEL ,  PAUPORTE ANDRE ,  SPAGNOL VICTOR ,  LEBIZAY GERALD ,  MUNIER JEAN-MARIE ,  SAINT-GEORGES ERIC

    IPC: H04L29/06

    Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.

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