公开(公告)号：JP2008135160A

公开(公告)日：2008-06-12

申请号：JP2007302031

申请日：2007-11-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： POZIDIS CHARALAMPOS ,  EVANGELOS S ELEFTHERIOU

IPC: G11B9/14

CPC classification number: G11B9/14 ,  B82Y10/00 ,  G11B11/007

Abstract: PROBLEM TO BE SOLVED: To provide methods and apparatus for recording/reproducing data in a device in which application of a write signal causes formation of an indentation on a storage surface by a probe of the probe-based data storage device.
SOLUTION: Information is stored in the form of grooves of variable length separated by lands of variable length. By applying a series of write signals at respective probe-positions on the storage surface, a first value (generally "1") which is a series of n>1 successive bits sequence in a recording signal is recoded. These probe-positions are spaced at w

Abstract translation: 要解决的问题：提供用于在写入信号的应用通过基于探测器的数据存储装置的探头在存储表面上形成凹陷的装置中记录/再现数据的方法和装置。

解决方案：信息以可变长度分隔的可变长度的槽的形式存储。 通过在存储表面上的相应探针位置应用一系列写信号，记录作为记录信号中的一系列n> 1个连续位序列的第一值（通常为“1”）被重新编码。 这些探针位置间距为w <= M，其中，M为压痕合并距离，以便产生的压痕合并，形成跨越n个回读采样位置的存储表面中的凹槽。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：GB2488057B

公开(公告)日：2017-12-06

申请号：GB201207470

申请日：2010-11-26

Applicant: IBM

Inventor： THEODORE A ANTONAKOPOULOS ,  ROY DARON CIDECIYAN ,  EVANGELOS S ELEFTHERIOU ,  ROBERT HAAS ,  XIAO-YU HU ,  ILIAS ILIADIS

IPC: G06F11/10 ,  G11C29/00

Abstract: Systems and methods are provided that confront the problem of failed storage integrated circuits (ICs) in a solid state drive (SSD) by using a fault-tolerant architecture along with one error correction code (ECC) mechanism for random/burst error corrections and an L-fold interleaving mechanism. The systems and methods described herein keep the SSD operational when one or more integrated circuits fail and allow the recovery of previously stored data from failed integrated circuits and allow random/burst errors to be corrected in other operational integrated circuits. These systems and methods replace the failed integrated circuits with fully functional/operational integrated circuits treated herein as spare integrated circuits. Furthermore, these systems and methods improve I/O performance in terms of maximum achievable read/write data rate.