公开(公告)号：GB2496798B

公开(公告)日：2016-10-12

申请号：GB201302858

申请日：2011-07-25

Applicant: IBM

Inventor： WERNER BUX ,  ROBERT HAAS ,  XIAOYU HU ,  ROMAN A PLETKA

IPC: G06F12/0886 ,  G06F12/02 ,  G06F12/0846 ,  G06F12/0866

公开(公告)号：GB2513492B

公开(公告)日：2018-07-11

申请号：GB201411668

申请日：2012-11-20

Applicant: IBM

Inventor： EVANGELOS STAVROS ELEFTHERIOU ,  ROBERT HAAS ,  NILS HAUSTEIN ,  JENS JELITTO ,  ALEXANDER SAUPP ,  HARALD SEIPP

IPC: G06F3/06 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0871 ,  G06F12/123

公开(公告)号：GB2488057B

公开(公告)日：2017-12-06

申请号：GB201207470

申请日：2010-11-26

Applicant: IBM

Inventor： THEODORE A ANTONAKOPOULOS ,  ROY DARON CIDECIYAN ,  EVANGELOS S ELEFTHERIOU ,  ROBERT HAAS ,  XIAO-YU HU ,  ILIAS ILIADIS

IPC: G06F11/10 ,  G11C29/00

Abstract: Systems and methods are provided that confront the problem of failed storage integrated circuits (ICs) in a solid state drive (SSD) by using a fault-tolerant architecture along with one error correction code (ECC) mechanism for random/burst error corrections and an L-fold interleaving mechanism. The systems and methods described herein keep the SSD operational when one or more integrated circuits fail and allow the recovery of previously stored data from failed integrated circuits and allow random/burst errors to be corrected in other operational integrated circuits. These systems and methods replace the failed integrated circuits with fully functional/operational integrated circuits treated herein as spare integrated circuits. Furthermore, these systems and methods improve I/O performance in terms of maximum achievable read/write data rate.

公开(公告)号：SG101997A1

公开(公告)日：2004-02-27

申请号：SG200105146

申请日：2001-08-23

Applicant: IBM

Inventor： ROBERT HAAS ,  PATRICK DROZ

IPC: H04L12/56 ,  G06F13/00 ,  H04L12/16 ,  H04L12/24 ,  H04L12/28

公开(公告)号：GB2488457B

公开(公告)日：2018-01-03

申请号：GB201207325

申请日：2010-12-16

Applicant: IBM

Inventor： ROY DARON CIDECIYAN ,  EVANGELOS STAVROS ELEFTHERIOU ,  ROBERT HAAS ,  XIAO-YU HU ,  ILIAS ILIADIS

IPC: G06F11/10

公开(公告)号：GB2513741B

公开(公告)日：2016-11-02

申请号：GB201409211

申请日：2012-10-19

Applicant: IBM

Inventor： LOKESH MOHAN GUPTA ,  EVANGELOS STRAVROS ELEFTHERIOU ,  IOANNIS KOLTSIDAS ,  XIAO-YU HU ,  ROMAN PLETKA ,  ROBERT HAAS ,  STEPHEN BLINICK ,  MICHAEL THOMAS BENHASE

IPC: G06F12/0888 ,  G06F12/0866 ,  G06F12/0897

公开(公告)号：GB2488462B

公开(公告)日：2018-01-17

申请号：GB201208241

申请日：2010-12-16

Applicant: IBM

Inventor： ROY DARON CIDECIYAN ,  EVANGELOS STAVROS ELEFTHERIOU ,  ROBERT HAAS ,  XIAO-YU HU ,  ILIAS ILIADIS ,  THOMAS MITTELHOLZER

IPC: G06F11/10

公开(公告)号：GB2490412B

公开(公告)日：2017-12-13

申请号：GB201207226

申请日：2011-01-07

Applicant: IBM

Inventor： ROMAN PLETKA ,  EVANGELOS ELEFTHERIOU ,  ROBERT HAAS ,  XIAO-YU HU ,  YU-CHENG HSU ,  LOKESH MOHAN GUPTA ,  JOSEPH SMITH HYDE II ,  MICHAEL THOMAS BENHASE ,  ALFRED EMILIO SANCHEZ ,  KEVIN JOHN ASH

IPC: G06F12/0866

Abstract: An I/O enclosure module is provided with one or more I/O enclosures having a plurality of slots for receiving electronic devices. A host adapter is connected a first slot of the I/O enclosure module and is configured to connect a host to the I/O enclosure. A device adapter is connected to a second slot of the I/O enclosure module and is configured to connect a storage device to the I/O enclosure module. A flash cache is connected to a third slot of the I/O enclosure module and includes a flash-based memory configured to cache data associated with data requests handled through the I/O enclosure module. A primary processor complex manages data requests handled through the I/O enclosure module by communicating with the host adapter, device adapter, and flash cache to manage to the data requests.

公开(公告)号：GB2485314B

公开(公告)日：2017-08-30

申请号：GB201202415

申请日：2010-08-30

Applicant: IBM

Inventor： ROBERT HAAS ,  JOHN GARANT ,  PHIL PALMATIER ,  BOUWE LEENSTRA

IPC: B23K3/06