-
公开(公告)号:GB2456405A
公开(公告)日:2009-07-22
申请号:GB0822457
申请日:2008-12-10
Applicant: IBM
Inventor: JACOBI CHRISTIAN , FABEL SIMON , PFLANZ MATTHIAS , TAST HANS-WERNER , ULRICH HANNO
IPC: G06F12/08 , G06F12/0855 , G06F12/0862 , G06F12/0893
Abstract: In a cache accessed under the control of a cache pipeline (14), store requests are managed in a store queue (10) and read requests are managed in a read queue (12), respectively, and prioritization logic (18) decides if a read request or a write request is to be forwarded to the cache pipeline (14). The prioritization logic (62) aborts a store request that has started if a fetch request arrives within a predetermined store abort window and grants cache access to the arrived fetch request. When the fetch request no longer requires the input stage of the cache pipeline, a control mechanism repeats the access control of the aborted store request for a further trial to access the pipeline (14). Preferably, the store abort window spans 3 to 7 cycles, preferably 4 or 5 cycles, and starts after 2 to 4 cycles, preferably 3 cycles.
-
公开(公告)号:GB2456405B
公开(公告)日:2012-05-02
申请号:GB0822457
申请日:2008-12-10
Applicant: IBM
Inventor: JACOBI CHRISTIAN , FABEL SIMON , PFLANZ MATTHIAS , TAST HANS-WERNER , ULRICH HANNO
IPC: G06F12/08 , G06F12/0855 , G06F12/0862 , G06F12/0893
-