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    CURVE GENERATION IN A DISPLAY SYSTEM
    4.
    发明专利
    CURVE GENERATION IN A DISPLAY SYSTEM 未知

    公开(公告)号：CA1309523C

    公开(公告)日：1992-10-27

    申请号：CA565450

    申请日：1988-04-29

    Applicant: IBM

    Inventor： CLARK DAVID A ,  FARR ROBERT W E

    IPC: G06T11/00 ,  G06T11/20 ,  G09G1/08 ,  G09G5/20 ,  G09G1/14

    Abstract: UK9-85-011 CURVE GENERATION IN A DISPLAY SYSTEM A curve generator for a display system comprises arc generation means for generating an arc of a circle from data defining the locations of two end points and an intermediate point on the arc. The arc generation means comprises initialisation means for calculating the angle subtended between a first vector, from a first of the end points to the intermediate point and a second vector from the second of the end points to the intermediate point and arc plotting means for defining a succession of further vectors from said first end point and for calculating, for each further vector, its point of intersection with a counterpart vector, from the second end point, with which it subtends said angle, whereby a succession of further points are plotted on the circular arc. The plotting logic thus plots the points of the arc with respect to a given point on the arc itself by generating vectors from that given point and enables the computation of the arc to be performed substantially within the system co-ordinate space in which the arc exists, which reduces the number of places of accuracy needed in order to accurately compute the arc.

    GRAPHICS DISPLAY TERMINAL AND METHOD OF STORING ALPHANUMERIC DATA THEREIN
    8.
    发明专利
    GRAPHICS DISPLAY TERMINAL AND METHOD OF STORING ALPHANUMERIC DATA THEREIN 未知

    公开(公告)号：CA1241780A

    公开(公告)日：1988-09-06

    申请号：CA483259

    申请日：1985-06-05

    Applicant: IBM

    Inventor： BOWATER RONALD J ,  DAVIS MICHAEL I ,  FARR ROBERT W E ,  POWELL COLIN V

    IPC: G06G7/163 ,  G09G5/06 ,  G09G3/00

    Abstract: The specification describes a method of storing alphanumeric characters (including special symbols) in a graphics display terminal comprising a raster-scan display device and a refresh buffer including a plurality of bit planes (1 to 6) each having a respective bit storage location corresponding to each addressible pel position on the screen of the display device. In the method, a first bit plane (luminance plane 1) stores high resolution luminance data defining alphanumeric characters each as a selection of "on" bits within a respective n x m array (character box) where n is the width of the character box in the scan line direction, and at least one further bit plane (attribute plane 2) stores low resolution colour data for the characters. The attribute plane (2) comprises a respective n-bit set of storage locations which corresponds to each n-bit wide by one pel deep portion of a character box in the luminance plane (1) and defines at least the colour and/or intensity of the foreground and background of the character for the width of the character box in respect of a single scan line. The specification also describes a graphics display terminal in which data in the luminance and attribute planes may be selectively decoded either as alphanumeric data stored as above, or as bit-mapped graphics data.

    IMAGE CORRECTION BY SELECTIVE PULSE STRETCHING IN RASTER-SCAN CRT
    9.
    发明专利
    IMAGE CORRECTION BY SELECTIVE PULSE STRETCHING IN RASTER-SCAN CRT 未知

    公开(公告)号：CA1210170A

    公开(公告)日：1986-08-19

    申请号：CA436050

    申请日：1983-09-02

    Applicant: IBM

    Inventor： JUDD IAN D ,  FARR ROBERT W E

    IPC: G09G5/36 ,  G09G1/00 ,  G09G3/20 ,  G09G5/00 ,  G09G5/24 ,  G09G5/32

    Abstract: In order to compensate for image distortion introduced into a digitally-controlled raster-scan CRT by the finite video amplifier rise and fall times, the digital video drive waveform is subject to selective pulse stretching to extend where possible the duration of pels which represent critical features of the image. This is achieved by decoding means for examining each pel at least in relation to its two immediate neighbours on either side in order to detect predetermined relationships between the values of the pels, and retiming means for selectively advancing or delaying the transitions between consecutive pels of different value in accordance with the relationships so detected. In one embodiment, suitable for multibit or single bit video, the decoding means comprises means for comparing each pel with its immediate successor, a shift register for storing the result of each comparison together with the results of a plurality of immediately preceding comparisons, and a logic circuit connected to the shift register stages, and the retiming means comprises a delay path for the waveform having an output register and means responsive to the logic circuit for clocking the output register at a predetermined time in relation to non-selected transitions, earlier than the said predetermined time in relation to transitions selected for advancement, and later than the said predetermined time in relation to transitions selected for delay.

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