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公开(公告)号：DE68920580D1
公开(公告)日：1995-02-23
申请号：DE68920580
申请日：1989-10-12
Applicant: IBM
Inventor： HAIGH DAVID CHRISTOPHER , FARR ROBERT WILLIAM ERIC
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公开(公告)号：DE3882269D1
公开(公告)日：1993-08-19
申请号：DE3882269
申请日：1988-03-17
Applicant: IBM
Inventor： CLARKE DAVID ANDREW , FARR ROBERT WILLIAM ERIC
Abstract: A curve generator for a display system comprises arc generation means for generating an arc 10 of a circle 14 from data defining the locations of two end points P1 and P3 and an intermediate point P2 on the arc. The arc generation means comprises initialisation means 40 for calculating the angle subtended between a first vector 21, from a first of the end points P1 to the intermediate point P2, and a second vector 32, from the second of the end points P3 to the intermediate point P2, and arc plotting means 44 for defining a succession of further vectors n1 from said first end point P1 and for calculating, for each further vector, its point of intersection Pn with a counterpart vector 3n, from said second end point P3, with which it subtends said angle, whereby a succession of further points Pn are plotted on the circular arc. The plotting logic thus plots the points of the arc with respect to a given point on the arc itself by generating vectors from that given point and enables the computation of the arc to be performed substantially within the system co-ordinate space in which the arc exists, which reduces the number of places of accuracy needed in order to accurately compute the arc.
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公开(公告)号：DE3475446D1
公开(公告)日：1989-01-05
申请号：DE3475446
申请日：1984-06-25
Applicant: IBM
Abstract: A terminal includes a raster-scan display device and a refresh buffer having bit planes (1-6) each with a respective bit storage location corresp. to each addressable pel position on the display screen. The bit planes are addressed in coordination with the line-by-line scanning of the display device to provide multi-bit per pel output data defining the colour and/or intensity of each pel on the screen. In order to store alphanumeric data on such a terminal, high resolution luminance data, defining alphanumeric characters each as a selection of 'on' bits within a respective character box, is stored in a bit plane (luminance plane 1). At least one further bit plane (attribute plane 2) is used to store low resolution colour data which defines at least the colour and/or intensity of the foreground and background of the characters.
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公开(公告)号：DE3882269T2
公开(公告)日：1994-02-17
申请号：DE3882269
申请日：1988-03-17
Applicant: IBM
Inventor： CLARKE DAVID ANDREW , FARR ROBERT WILLIAM ERIC
Abstract: A curve generator for a display system comprises arc generation means for generating an arc 10 of a circle 14 from data defining the locations of two end points P1 and P3 and an intermediate point P2 on the arc. The arc generation means comprises initialisation means 40 for calculating the angle subtended between a first vector 21, from a first of the end points P1 to the intermediate point P2, and a second vector 32, from the second of the end points P3 to the intermediate point P2, and arc plotting means 44 for defining a succession of further vectors n1 from said first end point P1 and for calculating, for each further vector, its point of intersection Pn with a counterpart vector 3n, from said second end point P3, with which it subtends said angle, whereby a succession of further points Pn are plotted on the circular arc. The plotting logic thus plots the points of the arc with respect to a given point on the arc itself by generating vectors from that given point and enables the computation of the arc to be performed substantially within the system co-ordinate space in which the arc exists, which reduces the number of places of accuracy needed in order to accurately compute the arc.
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Patent Agency Ranking
公开(公告)号：GB2204216B
公开(公告)日：1991-02-06
申请号：GB8710325
申请日：1987-04-30
Applicant: IBM
Inventor： CLARKE DAVID ANDREW , FARR ROBERT WILLIAM ERIC
Abstract: A curve generator for a display system comprises arc generation means for generating an arc 10 of a circle 14 from data defining the locations of two end points P1 and P3 and an intermediate point P2 on the arc. The arc generation means comprises initialisation means 40 for calculating the angle subtended between a first vector 21, from a first of the end points P1 to the intermediate point P2, and a second vector 32, from the second of the end points P3 to the intermediate point P2, and arc plotting means 44 for defining a succession of further vectors n1 from said first end point P1 and for calculating, for each further vector, its point of intersection Pn with a counterpart vector 3n, from said second end point P3, with which it subtends said angle, whereby a succession of further points Pn are plotted on the circular arc. The plotting logic thus plots the points of the arc with respect to a given point on the arc itself by generating vectors from that given point and enables the computation of the arc to be performed substantially within the system co-ordinate space in which the arc exists, which reduces the number of places of accuracy needed in order to accurately compute the arc.
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公开(公告)号：DE2339084A1
公开(公告)日：1974-05-02
申请号：DE2339084
申请日：1973-08-02
Applicant: IBM
Inventor： CAMERON JFAN RODERICK FRASER , FARR ROBERT WILLIAM ERIC
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公开(公告)号：DE68920580T2
公开(公告)日：1995-07-06
申请号：DE68920580
申请日：1989-10-12
Applicant: IBM
Inventor： HAIGH DAVID CHRISTOPHER , FARR ROBERT WILLIAM ERIC
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公开(公告)号：GB2204216A
公开(公告)日：1988-11-02
申请号：GB8710325
申请日：1987-04-30
Applicant: IBM
Inventor： CLARKE DAVID ANDREW , FARR ROBERT WILLIAM ERIC
Abstract: A curve generator for a display system comprises arc generation means for generating an arc 10 of a circle 14 from data defining the locations of two end points P1 and P3 and an intermediate point P2 on the arc. The arc generation means comprises initialisation means 40 for calculating the angle subtended between a first vector 21, from a first of the end points P1 to the intermediate point P2, and a second vector 32, from the second of the end points P3 to the intermediate point P2, and arc plotting means 44 for defining a succession of further vectors n1 from said first end point P1 and for calculating, for each further vector, its point of intersection Pn with a counterpart vector 3n, from said second end point P3, with which it subtends said angle, whereby a succession of further points Pn are plotted on the circular arc. The plotting logic thus plots the points of the arc with respect to a given point on the arc itself by generating vectors from that given point and enables the computation of the arc to be performed substantially within the system co-ordinate space in which the arc exists, which reduces the number of places of accuracy needed in order to accurately compute the arc.
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公开(公告)号：DE3270136D1
公开(公告)日：1986-04-30
申请号：DE3270136
申请日：1982-09-29
Applicant: IBM
Inventor： JUDD IAN DAVID , FARR ROBERT WILLIAM ERIC
Abstract: In order to compensate for image distortion introduced into a digitally-controlled raster-scan CRT by the finite video amplifier rise and fall times, the digital video drive waveform is subject to selective pulse stretching to extend where possible the duration of pels which represent critical features of the image. This is achieved by decoding means for examining each pel at least in relation to its two immediate neighbors on either side in order to detect predetermined relationships between the values of the pels, and retiming means for selectively advancing or delaying the transitions between consecutive pels of different value in accordance with the relationships so detected. In one embodiment, suitable for multibit or single bit video, the decoding means comprises means (40, 25) for comparing each pel with its immediate successor, a shift register (26 to 28) for storing the result of each comparison together with the results of a plurality of immediately preceding comparisons, and a logic circuit (30 to 33) connected to the shift register stages, and the retiming means comprises a delay path (41 to 44) for the waveform having an output register (44) and means (34 to 39) responsive to the logic circuit for clocking the output register at a predetermined time in relation to non-selected transitions, earlier than the said predetermined time in relation to transitions selected for advancement, and later than the said predetermined time in relation to transitions selected for delay.
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