中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

3 records (took 0.021 seconds)

    2.
    发明专利
    未知

    公开(公告)号：DE2231308A1

    公开(公告)日：1973-01-11

    申请号：DE2231308

    申请日：1972-06-26

    Applicant: IBM

    Inventor： FEATHERSTON JOHN RICHARD

    IPC: H04B1/50 ,  H04L1/00 ,  H04B7/00

    Abstract: The reliability and efficacy of traffic control in multiple station exigent radio communications is assured by a digital data communication system having accelerated polling and lockout of satellite or circumjacent subordinate station transmitting apparatus when the subordinate stations are contending for the attention of the central or base station and/or a circumjacent station is located in an area of unfavorable radio wave propagation. Duplex frequency operation with the central station continuously broadcasting messages and/or synchronizing characters, assures synchronization and resynchronization immediately on receipt of a single synchronizing character. Contention is evaluated in the central receiving apparatus by determining the level of optimum signal-to-noise ratio and measuring the r.m.s. value of distortion to establish reception parameters for controlling the mode of the radio net operation. A busy signal is then broadcast for locking out all transmission from the subordinate stations except for that one station accepted. Similarly an indication of field strength is obtained at subordinate station receiving apparatus by a threshold detector arranged to lock out the transmitting apparatus for propagation levels predetermined as unreliable and in a mobile situation to notify the operator to move the station to a better location for communication. Current flow in the second limiter stage of an FM receiver is suggested as a base measurement over a predetermined time period to prevent backlash. Confirmation, acknowledgment, and roll call are controlled by a polling character transmitted at the end of a message. Circuitry responsive to these characters is arranged for conducting an accelerated poll for effecting a single bit response from each circumjacent transmitter addressed specifically in a poll as listed in a predetermined time assignment. For the latter arrangement a shift register used for normal data processing is arranged to double as a counter for this purpose. Changeover delay is obviated by effecting transmission at a predetermined later bit time. Subordinate stations are addressed in general, in groups or as individual stations as best suits the purpose at the central station. Each character comprises identification bits and a control bit. Circuitry responsive to the latter bit is arranged to lock out the transmitter when the central receiving apparatus is busy. Overall capacity of the system is enhanced by interposing message buffer stores for each transmitting and each receiving apparatus.

    3.
    发明专利
    未知

    公开(公告)号：DE1279780B

    公开(公告)日：1968-10-10

    申请号：DEJ0021415

    申请日：1962-03-10

    Applicant: IBM

    Inventor： FEATHERSTON JOHN RICHARD

    IPC: H04L1/06

    Abstract: 1,000,606. Diversity reception systems. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 13, 1962 [March 13, 1961], No. 9601/62. Heading H4L. A diversity reception system for data signals in the form of time-spaced coded pulse groups is provided with means for selecting the channel providing the strongest signal and for ensuring that the changeover from one channel to another takes place only during the space between code groups. The system may operate with space, frequency or polarization diversity. As shown, radio receivers 10, 11 receive the same pulse signals from spaced aerials which after demodulation at 34, 35 are passed to respective AND gates 38, 39. A.g.c. signals from the two receivers are applied to respective D.C. amplifiers 18, 19 supplying a differential amplifier 20 and the output of the amplifier 20 controls a Schmitt trigger 22 which provides a certain amount of " backlash " so that changeover only takes place if there is a significant difference between received signals. The complementary outputs of the trigger 22 are supplied to AND gates 26, 27 respectively together with clock pulses C o from a bit ring 58. The pulse groups are arranged so that the first digit is always 0 to provide a blank between groups and it is identified by clock pulse C 0 . The output data pulses from OR gate 46 are supplied to a bit synchronizer 50 generating timing pulses controlling the counter 58. The data output pulses are also passed to a shift register 52 and stepped therethrough under control of the clock pulses from 50. Before reception is started a unique character is set up in a register 54 which is coupled to a comparison unit 56 so that when that unique character is received at the start of a data signal, a reset pulse is applied to the counter 58 to synchronize clock pulses C o to C, with the incoming signals. AND gates 26, 27 control a bi-stable device 32 providing respective inputs to open either AND gate 38 or 39. The data signals from the selected channel are passed via OR gate 46 to utilization means 49 controlled by the clock pulses C o to C 7 .

Patent Agency Ranking