公开(公告)号：US3892925A

公开(公告)日：1975-07-01

申请号：US47568274

申请日：1974-06-03

Applicant: IBM

Inventor： FISK DALE EDWARD ,  HOMAN MERLE EDWARD ,  MEILEY CHARLES LAURIE ,  REYNOLDS ZACK DWAYNE ,  WATKINS ROBERT VERNON ,  WIEDMER FRITZ S

IPC: H04Q3/52 ,  H04Q11/04 ,  H04J3/02

CPC classification number: H04Q11/04

Abstract: A multiple of telephone or like communications signal transmission lines are interconnected in time division multiplex (TDM) mode by integrated semiconductor switching circuitry. Preferably, electronic solid state structure most suitable for embodying field effect transistors (FET) and like associated devices is arranged in modular chip components permitting extension to large numbers of transmission lines, as desired. Input or calling transmission line terminals are connected to node busses by FET switches in predetermined time sequence under control of a central processing unit. Preferably, a separate timing pulse train generating circuit is used for the switching operation. Output or called transmission line terminals are connected to the node busses in predetermined time sequence at which every calling line is sampled at least once each switching cycle. Signal bandwidth is adjustable by arranging the switching circuitry to sample a calling line one, two, or more times in each switching cycle. Conventional semiconductor structure inherently forms capacitors of substantial reactance between the node busses and points of reference potential. Circuitry is incorporated in the arrangement for discharging the capacitors prior to connecting the input signal lines to the node busses. The circuitry also incorporates FET switch elements arranged for isolating uncalled output terminals from the switching circuitry, and for short circuiting each pair of idle output terminals.

Abstract translation: 电话或类似通信信号传输线路的多个通过集成半导体开关电路以时分复用（TDM）模式相互连接。 优选地，根据需要，最适于体现场效应晶体管（FET）等相关器件的电子固态结构被布置在允许扩展到大量传输线的模块化芯片组件中。 在中央处理单元的控制下，输入或呼叫传输线路终端通过FET开关以预定的时间顺序连接到节点总线。 优选地，单独的定时脉冲串生成电路用于切换操作。 输出或称为传输线路终端以预定的时间顺序连接到节点总线，每个呼叫线路在每个切换周期至少采样一次。 信号带宽可通过安排开关电路在每个开关周期中对一个或两个或更多次的呼叫线路进行采样来调整。 常规的半导体结构固有地形成节点总线和参考点之间的实质电抗的电容器。 在将输入信号线连接到节点总线之前，将电路并入用于放电电容器的布置。 该电路还包括FET开关元件，用于将不需要的输出端子与开关电路隔离，并且用于短路每对空闲输出端子。

公开(公告)号：DE3377969D1

公开(公告)日：1988-10-13

申请号：DE3377969

申请日：1983-06-21

Applicant: IBM

Inventor： FEATHERSTON JOHN RICHARD ,  HOPNER EMIL ,  PATTEN MICHAEL ALLEN ,  WATKINS ROBERT VERNON

IPC: H04Q3/52 ,  H04Q11/04 ,  H04Q3/495

公开(公告)号：DE2523398A1

公开(公告)日：1975-12-04

申请号：DE2523398

申请日：1975-05-27

Applicant: IBM

Inventor： FISK DALE EDWARD ,  HOMAN MERLE EDWARD ,  MEILEY CHARLES LAURIE ,  REYNOLDS ZACK DWAYNE ,  WATKINS ROBERT VERNON ,  WIEDMER FRITZ SIMON

IPC: H04Q3/52 ,  H04Q11/04

Abstract: A multiple of telephone or like communications signal transmission lines are interconnected in time division multiplex (TDM) mode by integrated semiconductor switching circuitry. Preferably, electronic solid state structure most suitable for embodying field effect transistors (FET) and like associated devices is arranged in modular chip components permitting extension to large numbers of transmission lines, as desired. Input or calling transmission line terminals are connected to node busses by FET switches in predetermined time sequence under control of a central processing unit. Preferably, a separate timing pulse train generating circuit is used for the switching operation. Output or called transmission line terminals are connected to the node busses in predetermined time sequence at which every calling line is sampled at least once each switching cycle. Signal bandwidth is adjustable by arranging the switching circuitry to sample a calling line one, two, or more times in each switching cycle. Conventional semiconductor structure inherently forms capacitors of substantial reactance between the node busses and points of reference potential. Circuitry is incorporated in the arrangement for discharging the capacitors prior to connecting the input signal lines to the node busses. The circuitry also incorporates FET switch elements arranged for isolating uncalled output terminals from the switching circuitry, and for short circuiting each pair of idle output terminals.