公开(公告)号：GB2560480A

公开(公告)日：2018-09-12

申请号：GB201810430

申请日：2016-11-22

Applicant: IBM

Inventor： FEI LIU ,  QING CAO ,  KANGGUO CHENG ,  ZHENGWEN LI

IPC: G06N3/063 ,  G06N3/04

Abstract: A three-dimensional integration of synapse circuitry is formed. One or more neuron layers each comprises a plurality of computing elements, and one or more synapse layers each comprising an array of memory elements are formed on top of the one or more neuron layers. A plurality of staggered through-silicon vias (TSVs) connect the one or more neuron layers to the one or more synapse layers and operate as communication links between one or more computing elements in the one or more neuron layers and one or more memory elements in the one or more synapse layers.