公开(公告)号：GB2635490A

公开(公告)日：2025-05-14

申请号：GB202504146

申请日：2023-05-18

Applicant: IBM

Inventor： JUNTAO LI ,  KANGGUO CHENG ,  CARL RADENS ,  CHING-TZU CHEN

IPC: H10N70/20 ,  H10B63/10

Abstract: A phase change memory structure with improved sidewall heater and formation thereof may be presented. Phase change materials are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in the active region of the cell. Presented herein may be a side wall heater, where the upper section extends through bilayer dielectric to contact a phase change material layer and the lower section of the sidewall heater has conductive layers in contact with the bottom electrode. The width of the sidewall heater may reflect an inverted T shape reducing the current requirement to reset the phase change material.

公开(公告)号：GB2603283A

公开(公告)日：2022-08-03

申请号：GB202117763

申请日：2021-12-09

Applicant: IBM

Inventor： JULIEN FROUGIER ,  RUILONG XIE ,  KANGGUO CHENG ,  CHANRO PARK

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A method including: forming a source/drain on an exposed portion of a semiconductor layer 123,126 of a layered nanosheet; forming a sacrificial material on the source/drain; forming a dielectric layer 205 covering the sacrificial material; and replacing the sacrificial material with a contact liner 240. Also disclosed is a semiconductor device including: a first gate nanosheet stack and second gate nanosheet stack; a first source/drain in contact with the first nanosheet stack and a second source/drain in contact with the second nanosheet stack; a source/drain dielectric 205 located between the first source/drain and the second source/drain; and a contact liner 240 in contact with the first source/drain, the second source/drain and the source/drain dielectric 205. Further disclosed is the method of forming the semiconductor device using the above method.

公开(公告)号：GB2550740B

公开(公告)日：2020-05-20

申请号：GB201712260

申请日：2016-01-04

Applicant: IBM

Inventor： BRUCE DORIS ,  KERN RIM ,  ALEXANDER REZNICEK ,  DARSEN DUANE LU ,  ALI KHAKIFIROOZ ,  KANGGUO CHENG

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66

Abstract: A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the SSOI structure, forming a gate structure over a portion of at least one fin in a nFET region, forming a gate structure over a portion of at least one fin in a pFET region, removing the gate structure over the portion of the at least one fin in the pFET region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pFET region, such that the new gate structure surrounds the portion on all four sides.

公开(公告)号：GB2517854B

公开(公告)日：2016-08-31

申请号：GB201419746

申请日：2013-03-13

Applicant: IBM

Inventor： BRUCE B DORIS ,  KANGGUO CHENG ,  BALASUBRAMANIAN HARAN ,  ALI KHAKIFIROOZ ,  PRANITA KULKARNI ,  ARVIND KUMAR ,  SHOM PONOTH

IPC: H01L21/762 ,  H01L21/8238

公开(公告)号：GB2494338A

公开(公告)日：2013-03-06

申请号：GB201221985

申请日：2011-03-31

Applicant: IBM

Inventor： BOOTH ROGER A ,  KANGGUO CHENG ,  PEI CHENGWEN ,  FURUKAWA TOSHIHARU

IPC: H01L27/06 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L29/94

Abstract: An integrated circuit having finFETs(60a,b) and a metal-insulator-metal (MIM) fin capacitor (65) and methods of manufacture are disclosed. A method includes forming a first finFET (60a) comprising a first dielectric (25) and a first conductor (30); forming a second finFET (60b) comprising a second dielectric (40) and a second conductor (45); and forming a fin capacitor (65) comprising the first conductor (25), the second dielectric (40), and the second conductor (45).

公开(公告)号：GB2634478A

公开(公告)日：2025-04-09

申请号：GB202500991

申请日：2023-07-31

Applicant: IBM

Inventor： CHANRO PARK ,  JULIEN FROUGIER ,  RUILONG XIE ,  KANGGUO CHENG

IPC: H10B63/00 ,  H10N70/20

Abstract: A non-volatile memory having a 3D cross-point architecture and twice the cell density is provided in which vertically stacked word lines run in plane (i.e., parallel) to the substrate and bit lines runs perpendicular to the vertically stacked word lines. The vertically stacked word lines are located in a patterned dielectric material stack that includes alternating first dielectric material layers and recessed second dielectric material layers. The first dielectric material layers vertically separate each word line within each vertical stack of word lines and the recessed second dielectric material layers are located laterally adjacent to the word lines. A dielectric switching material layer is located between each word line-bit line combination. Some of the bit lines are located in the dielectric material stack and some of the bit lines are located in an interlayer dielectric material layer.

公开(公告)号：GB2631071A

公开(公告)日：2024-12-18

申请号：GB202414743

申请日：2023-03-23

Applicant: IBM

Inventor： JULIEN FROUGIER ,  RUILONG XIE ,  KANGGUO CHENG ,  CHANRO PARK ,  OLEG GLUSCHENKOV

IPC: H01L29/08 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor structure is presented including source/drain (S/D) epitaxial growth formed over a bottom dielectric isolation region, at least one first semiconductor layer disposed within the S/D epitaxial growth in a S/D region and at least one second semiconductor layer disposed partially within a gate region. The at least one second semiconductor layer extends from the gate region into a spacer region to enable a connection to the S/D epitaxial growth. The semiconductor structure further includes a first region with adjacent devices exhibiting a first Contacted gate Poly Pitch (CPP) defining a first gate-to-gate space and a second region with adjacent devices exhibiting a second CPP defining a second gate-to-gate space, where adjacent devices exhibiting the first CPP have a smaller gate-to-gate canyon than the adjacent devices exhibiting the second CPP such that the second gate-to-gate space is greater than the first gate-to-gate space.

公开(公告)号：GB2600316B

公开(公告)日：2023-05-24

申请号：GB202200795

申请日：2020-06-15

Applicant: IBM

Inventor： RUILONG XIE ,  CARL RADENS ,  KANGGUO CHENG ,  VEERARAGHAVAN BASKER

IPC: H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H10B10/00

Abstract: A method of forming a semiconductor structure includes forming fins over a substrate, forming a shallow trench isolation region over the substrate surrounding the fins, and forming nanosheet stacks providing channels for nanosheet field-effect transistors. The method also includes forming a channel protecting liner over a portion of sidewalls and a top surface of a first nanosheet stack formed over a first fin, the channel protecting liner being further formed over a portion of the shallow trench isolation region extending from the sidewalls of the first nanosheet stack toward a second nanosheet stack formed over a second fin. The method further includes forming gate stacks surrounding exposed portions of the nanosheet stacks, forming an asymmetric self-aligned gate isolation structure over the channel protecting liner, and forming a symmetric self-aligned gate isolation structure over a portion of the shallow trench isolation region between a third fin and a fourth fin.

公开(公告)号：GB2603283B

公开(公告)日：2023-01-18

申请号：GB202117763

申请日：2021-12-09

Applicant: IBM

Inventor： JULIEN FROUGIER ,  RUILONG XIE ,  KANGGUO CHENG ,  CHANRO PARK

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: An embodiment includes a method of forming a semiconductor device and the resulting device. The method may include forming a source/drain on an exposed portion of a semiconductor layer of a layered nanosheet. The method may include forming a sacrificial material on the source/drain. The method may include forming a dielectric layer covering the sacrificial material. The method may include replacing the sacrificial material with a contact liner. The semiconductor device may include a first gate nanosheet stack and second gate nanosheet stack. The semiconductor device may include a first source/drain in contact with the first nanosheet stack and a second source/drain in contact with the second nanosheet stack. The semiconductor device may include a source/drain dielectric located between the first source/drain and the second source/drain. The semiconductor device may include a contact liner in contact with the first source/drain, the second source/drain and the source/drain dielectric.

公开(公告)号：GB2595125B

公开(公告)日：2022-11-09

申请号：GB202111358

申请日：2020-02-24

Applicant: IBM

Inventor： RUILONG XIE ,  JULIEN FROUGIER ,  CHANRO PARK ,  EDWARD NOWAK ,  YI QI ,  KANGGUO CHENG ,  NICOLAS JEAN LOUBET

IPC: H01L29/41

Abstract: Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack can include one or more first semiconductor layers and one or more first sacrificial layers. A trench is formed by removing a portion of the one or more first semiconductor layers and the one or more first sacrificial layers. The trench exposes a surface of a bottommost sacrificial layer of the one or more first sacrificial layers. The trench can be filled with one or more second semiconductor layers and one or more second sacrificial layers such that each of the one or more second semiconductor layers is in contact with a sidewall of one of the one or more first semiconductor layers.