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1.发明申请METHOD AND APPARATUS FOR DETECTING CLOCK GATING OPPORTUNITIES IN A PIPELINED ELECTRONIC CIRCUIT DESIGN 审中-公开用于检测管道电子电路设计中的时钟增益机会的方法和装置
公开(公告)号：WO2009024540A3
公开(公告)日：2009-09-17
申请号：PCT/EP2008060722
申请日：2008-08-14
Applicant: IBM , FERNSLER MATTHEW EARL , JACOBSON HANS MIKAEL , SROUJI JOHNY , SWANSON TODD
Inventor： FERNSLER MATTHEW EARL , JACOBSON HANS MIKAEL , SROUJI JOHNY , SWANSON TODD
IPC: G06F1/32
CPC classification number: G06F1/3203 , G06F1/3237 , G06F9/3867 , Y02D10/128
Abstract: A pipeline electronic circuit and design methodology enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit to achieve power conservation by incorporating clock- gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.
Abstract translation: 管道电子电路和设计方法通过模拟来识别流水线各阶段之间的时钟门控机会，从而在管线的阶段实现功率节省。 在一个实施例中，模拟结果帮助设计者设计流水线电子电路，以通过在模拟识别的时钟门控机会位置处在管线的阶段之间并入时钟门控电路来实现功率节省。
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公开(公告)号：DE602008006561D1
公开(公告)日：2011-06-09
申请号：DE602008006561
申请日：2008-08-14
Applicant: IBM
Inventor： FERNSLER MATTHEW EARL , JACOBSON HANS MIKAEL , SROUJI JOHNY , SWANSON TODD
IPC: G06F1/32
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