Abstract:
A system and method for communicating instructions and data between a processor and external devices are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power "stall" state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
Abstract:
PROBLEM TO BE SOLVED: To provide a system and a method for communicating command parameters between a processor and a memory flow controller. SOLUTION: This application utilizes a channel interface as a main mechanism for communication between the processor and the memory flow controller. The channel interface provides a channel for executing communication with, for instance, a processor facility, a memory flow control facility, a machine status register, and an external processor interrupt facility. When data to be read from a corresponding register by a blocking channel are not usable or there is no writing space in the corresponding register, the processor is brought into a low-power "stall" state. When the data are made usable or a space is released, the processor is automatically called via communication on the blocking channel. COPYRIGHT: (C)2007,JPO&INPIT
Abstract:
A pipeline electronic circuit and design methodology enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit to achieve power conservation by incorporating clock- gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.