公开(公告)号：DE3278948D1

公开(公告)日：1988-09-29

申请号：DE3278948

申请日：1982-10-26

Applicant: IBM

Inventor： FLETCHER ROBERT PERCY ,  STEIN DAVID MORRIS ,  WLADAWSKY-BERGER IRVING

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F15/16 ,  G06F15/177

公开(公告)号：DE3279113D1

公开(公告)日：1988-11-17

申请号：DE3279113

申请日：1982-10-18

Applicant: IBM

Inventor： FLETCHER ROBERT PERCY ,  MARTIN DANIEL BOND

IPC: G06F12/08 ,  G06F12/10

Abstract: Cache class addressing controls are improved by modifying the congruence class addresses in a manner that distributes data accessed from storage pages more uniformly among the plurality of the cache congruence classes. The value of at least the lowest-order bit (19) in the external page address field in the CPU requested address is used to control the inversion of the second highest-order bit position (21) in a congruence class selection field which is obtained from the highorder part of the internal page address field in the CPU requested address. Thus a congruence class address (CCA) is generated that tends to smooth the fregency distribution of class use in a cache directory, thereby reducing the cache miss rate and correspondingly improving processor performance.

公开(公告)号：DE3278587D1

公开(公告)日：1988-07-07

申请号：DE3278587

申请日：1982-06-15

Applicant: IBM

Inventor： FLETCHER ROBERT PERCY

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/12

Abstract: The replacement selection of entries in a second level (L2) cache directory of a storage hierarchy is controlled using replaced and hit addresses of a dynamic look-aside translation buffer (DLAT) at the first level (L1) in the hierarchy which receives CPU storage requests along with the CPU cache and its directory. The DLAT entries address page size blocks in main storage (MS). The disclosure provides a replacement (R) flag for each entry in the L2 directory, which represents a page size block in the L2 cache. An R bit is selected and turned on by the address of a DLAT replaced page which is caused by a DLAT miss to indicate its associated page is a candidate for replacement in the L2 cache. However, the page may continue to be accessed in the L2 cache until it is actually replaced. An R bit is selected and turned off by a CPU request address causing a DLAT hit and a L1 cache miss to indicate its associated L2 page is not a candidate for replacement. When a small proportion of CPU requests bypass of the DLAT (e.g. real address requests), a L1 request address having a L1 cache miss may be used to turn off the R bit, and any replaced line address may be used to turn on the R bit, for the L2 entry selected by that address. L2 LRU replacement selection circuits generate a LRU pointer to another entry in the congruence class of the selected entry when its R flag is change from a no replacement state to a replacement state. Each turn off signal to an R flag may generate a new LRU pointer for its congruence class which also points away from the selected entry.

公开(公告)号：DE3278863D1

公开(公告)日：1988-09-08

申请号：DE3278863

申请日：1982-11-16

Applicant: IBM

Inventor： FLETCHER ROBERT PERCY

IPC: G06F12/08

公开(公告)号：DE3373569D1

公开(公告)日：1987-10-15

申请号：DE3373569

申请日：1983-02-04

Applicant: IBM

Inventor： FLETCHER ROBERT PERCY

IPC: G06F12/12 ,  G06F12/08 ,  G06F15/16

Abstract: Cache directory entry replacement for central processors (CPs) in a multiprocessor (MP) utilizes task identifiers (TIDs) provided in each directory entry to identify the program task which inserted the respective entry. A remote TID register (11) is provided to receive the TID from any remote CP in the MP on each cache miss cross-interrogation hit from any remote CP. Each time a respective CP (i.e. local CP) makes a storage request to its private cache directory, the TIDs are compared (in 18) to any remote TID in the CP's remote TID register. A TID candidate is any entry which compares equal to the remote TID and is not equal to the current local processor TID. It is identified as a candidate for replacement in the local cache directory on a cache miss. The candidate priorities in replacement selection circuit (51) are; highest priority is any invalid entry, next is any TID candidate, and lowest priority is the conventional LRU candidate. The TID operation obtains early castout to main storage of any cache line associated with a task being executed in a remote CP and not associated with the task being executed in the CP casting out the line, and thus reduces the potential for future cross-interrogation hits.

公开(公告)号：DE3277249D1

公开(公告)日：1987-10-15

申请号：DE3277249

申请日：1982-03-04

Applicant: IBM

Inventor： FLETCHER ROBERT PERCY

IPC: G06F12/08 ,  G06F15/16

Abstract: In a multiprocessor, each processor (4, 6) has its own high speed store in buffer (SIB) cache (8, 24) and each processor shares a common cache (10) with the other processors direct data paths (14, 28) interconnecting the common cache and the private caches. The control system ensures that all processors access the most up-to-date copy of memory information with a minimal performance impact, allowing only read only copies of the same shared memory block (line) to exist simultaneously in all private caches. Lines that are both shared and changed are stored in the common shared cache, which each processor can directly fetch from and store into. In a general system the cache manager dynamically detects and moves lines, which are both shared and changed, over direct interconnecting data paths (14, 25) to the common shared cache and returning, by cast out, lines from the shared cache once sharing has most probably ceased. A simplified system for structured applications is disclosed.