-
公开(公告)号:DE3278948D1
公开(公告)日:1988-09-29
申请号:DE3278948
申请日:1982-10-26
Applicant: IBM
Inventor: FLETCHER ROBERT PERCY , STEIN DAVID MORRIS , WLADAWSKY-BERGER IRVING
IPC: G06F12/00 , G06F12/02 , G06F12/08 , G06F15/16 , G06F15/177
-
公开(公告)号:IT1151066B
公开(公告)日:1986-12-17
申请号:IT2260680
申请日:1980-06-06
Applicant: IBM
Inventor: SCHORR HERBERT , WLADAWSKY-BERGER IRVING
Abstract: In a computer system the operating speed is increased by increasing the number of general registers (4) with a plurality of implicit registers (9) in an associative memory (3). An instruction (6) generated in a processing unit (1) for data access provides parameter words, such as base and displacement words, to be used as search arguments for an associative search for data in the implicit registers. If a match occurs, the data from the selected register is transferred to the processing unit (1) and the address generation started by the instruction for a memory (2) access is terminated.
-
公开(公告)号:IT8022606D0
公开(公告)日:1980-06-06
申请号:IT2260680
申请日:1980-06-06
Applicant: IBM
Inventor: SCHORR HERBERT , WLADAWSKY-BERGER IRVING
Abstract: In a computer system the operating speed is increased by increasing the number of general registers (4) with a plurality of implicit registers (9) in an associative memory (3). An instruction (6) generated in a processing unit (1) for data access provides parameter words, such as base and displacement words, to be used as search arguments for an associative search for data in the implicit registers. If a match occurs, the data from the selected register is transferred to the processing unit (1) and the address generation started by the instruction for a memory (2) access is terminated.
-
-