公开(公告)号：SG63818A1

公开(公告)日：1999-03-30

申请号：SG1998000434

申请日：1998-02-26

Applicant: IBM

Inventor： FLYNN WILLIAM THOMAS III ,  HILLIER PHILIP ROGERS III

IPC: G06F9/38 ,  G06F9/46

Abstract: The method and apparatus for decreasing thread switch latency in a multithread processor stores instructions for an active thread in a primary instruction queue, and stores instructions for a dormant thread in a thread switch instruction queue. The active thread is the thread currently being processed by the multithread processor, while the dormant thread is a thread not currently being executed by the multithread processor. During execution of the active thread, instructions are dispatched from the primary instruction queue for processing. When a thread switch occurs, instructions are dispatched from the thread switch instruction queue for execution. Simultaneously, instructions stored in the thread switch instruction queue are transferred to the primary instruction queue. In this manner, the thread switch latency resulting from the amount of time to refill the primary instruction queue with instructions of the dormant thread is eliminated.