公开(公告)号：GB2492620A

公开(公告)日：2013-01-09

申请号：GB201208064

申请日：2012-05-09

Applicant: IBM

Inventor： TRI STEVEN MICHAEL ,  O'CONNOR JAMES ,  HOLLAND WILLIAM GAVIN ,  ENGEBRETSEN DAVID ,  HUGHES JAMES EDWARD ,  ARMSTRONG WILLIAM JOSEPH ,  CRIPPEN MARTIN JOSEPH ,  DESAI DHRUV MANMOHANDAS ,  BORKENHAGEN JOHN MICHAEL ,  HILLIER PHILIP ROGERS III ,  PATEL PRAVIN

IPC: G06F13/40 ,  H04L69/40

Abstract: In a switching system (fig. 1) comprising server card â bladesâ (104, fig. 1 & 202, fig. 6), a midplane 123 is connected to switch modules 4201-3 on different server cards thus providing a fabric interconnect for a switch fabric under the operation of a management controller (1604, fig. 16) which updates and monitors the switch modules, and informs others when one fails. Switch modules may be replaced (â hot swappedâ ) without restarting the system or fabric.

公开(公告)号：SG63818A1

公开(公告)日：1999-03-30

申请号：SG1998000434

申请日：1998-02-26

Applicant: IBM

Inventor： FLYNN WILLIAM THOMAS III ,  HILLIER PHILIP ROGERS III

IPC: G06F9/38 ,  G06F9/46

Abstract: The method and apparatus for decreasing thread switch latency in a multithread processor stores instructions for an active thread in a primary instruction queue, and stores instructions for a dormant thread in a thread switch instruction queue. The active thread is the thread currently being processed by the multithread processor, while the dormant thread is a thread not currently being executed by the multithread processor. During execution of the active thread, instructions are dispatched from the primary instruction queue for processing. When a thread switch occurs, instructions are dispatched from the thread switch instruction queue for execution. Simultaneously, instructions stored in the thread switch instruction queue are transferred to the primary instruction queue. In this manner, the thread switch latency resulting from the amount of time to refill the primary instruction queue with instructions of the dormant thread is eliminated.

公开(公告)号：GB2491496A

公开(公告)日：2012-12-05

申请号：GB201212302

申请日：2011-03-11

Applicant: IBM

Inventor： SHEDIVY DAVID ALAN ,  HILLIER PHILIP ROGERS III ,  VALK KENNETH MICHAEL

IPC: G06F13/40 ,  H04L12/56

Abstract: A method and circuit for implementing enhanced link bandwidth for a headless interconnect chip in a local rack interconnect system, and a design structure on which the subject circuit resides are provided. The headless interconnect chip includes a cut through switch and a store and forward switch. A packet is received from an incoming link to be transmitted on an outgoing link on the headless interconnect chip. Both the cut through switch and the store and forward switch are selectively used for moving packets received from the incoming link to the outgoing link on the headless interconnect chip.

公开(公告)号：GB2512015A

公开(公告)日：2014-09-24

申请号：GB201209549

申请日：2011-02-18

Applicant: IBM

Inventor： SHEDIVY DAVID ALAN ,  HILLIER PHILIP ROGERS III ,  VALK KENNETH MICHAEL ,  FLYNN WILLIAM THOMAS

IPC: G06F13/40

Abstract: A method and circuit for implementing ordered and reliable transfer of packets while spraying packets over multiple links, and a design structure on which the subject circuit resides are provided. Each source interconnect chip maintains a spray mask including multiple available links for each destination chip for spraying packets across multiple links of a local rack interconnect system. Each packet is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The destination interconnect chip uses the ETE sequence numbers to reorder the received sprayed packets into the correct order before sending the packets to the destination device.

公开(公告)号：GB2492620B

公开(公告)日：2013-06-05

申请号：GB201208064

申请日：2012-05-09

Applicant: IBM

Inventor： TRI STEVEN MICHAEL ,  O'CONNOR JAMES ,  HOLLAND WILLIAM GAVIN ,  ENGEBRETSEN DAVID ,  HUGHES JAMES EDWARD ,  ARMSTRONG WILLIAM JOSEPH ,  CRIPPEN MARTIN JOSEPH ,  DESAI DHRUV MANMOHANDAS ,  BORKENHAGEN JOHN MICHAEL ,  HILLIER PHILIP ROGERS III ,  PATEL PRAVIN

IPC: G06F13/40 ,  H04L69/40

Abstract: Techniques are disclosed for managing a switch fabric. In one embodiment, a server system is provided that includes a midplane, one or more server cards, switch modules and a management controller. The midplane may include a fabric interconnect for a switch fabric. The one or more server cards and the switch modules may be operatively connected to the midplane. The switch modules may be configured to switch network traffic for the one or more server cards. The management controller may be configured to manage the switch modules via the fabric interconnect.

公开(公告)号：HK1011567A1

公开(公告)日：1999-07-16

申请号：HK98112653

申请日：1998-12-02

Applicant: IBM

Inventor： FLYNN WILLIAM THOMAS ,  HILLIER PHILIP ROGERS III

IPC: G06F9/38 ,  G06F9/46 ,  G06F

Abstract: The method and apparatus for decreasing thread switch latency in a multithread processor stores instructions for an active thread in a primary instruction queue, and stores instructions for a dormant thread in a thread switch instruction queue. The active thread is the thread currently being processed by the multithread processor, while the dormant thread is a thread not currently being executed by the multithread processor. During execution of the active thread, instructions are dispatched from the primary instruction queue for processing. When a thread switch occurs, instructions are dispatched from the thread switch instruction queue for execution. Simultaneously, instructions stored in the thread switch instruction queue are transferred to the primary instruction queue. In this manner, the thread switch latency resulting from the amount of time to refill the primary instruction queue with instructions of the dormant thread is eliminated.