公开(公告)号：MY107143A

公开(公告)日：1995-09-30

申请号：MYPI19901410

申请日：1990-08-22

Applicant: IBM

Inventor： JOSEPH PATRICK MCGOVERN ,  FRANCIS MICHAEL BONEVENTO ,  EUGENE MITCHELL THOMAS

IPC: G06F13/42 ,  G06F5/06 ,  G06F15/16

Abstract: A MICROPROCESSOR SYSTEM WHICH INCLUDES A PROCESSOR UNIT WITH SYSTEM MEMORY AND A SEPARATE BUFFER MEMORY, ONE OR MORE SUBSYSTEM ADAPTER UNITS WITH MEMORY, OPTIONAL I/O DEVICES WHICH MAY ATTACH TO THE ADAPTERS, AND A BUS INTERFACE. THE MEMORY IN THE PROCESSOR AND THE MEMORY IN THE ADAPTERS ARE USED BY THE SYSTEM AS A SHARED MEMORY WHICH IS CONFIGURED AS A DISTRIBUTED FIFO CIRCULAR QUEUE (A PIPE). UNIT TO UNIT ASYNCHRONOUS COMMUNICATION IS ACCOMPLISHED BY PLACING CONTROL ELEMENTS ON THE PIPE WHICH REPRESENT REQUESTS, REPLIES, AND STATUS INFORMATION. THE UNITS SEND AND RECEIVE CONTROL ELEMENTS INDEPENDENT OF THE OTHER UNITS WHICH ALLOWS FREE FLOWING ASYNCHRONOUS DELIVERY OF CONTROL INFORMATION AND DATA BETWEEN UNITS. THE SHARED MEMORY CAN BE ORGANIZED AS PIPE PAIRS BETWEEN EACH PAIR OF UNITS TO ALLOW FULL DUPLEX OPERATION BY USING ONE PIPE FOR OUTBOUND CONTROL ELEMENTS AND THE OTHER PIPE FOR INBOUND CONTROL ELEMENTS. THE CONTROL ELEMENTS HAVE STANDARD FIXED HEADER FIELDS WITH VARIABLE FIELDS FOLLOWING THE FIXED HEADER. THE FIXED HEADER ALLOWS A COMMON INTERFACE PROTOCOL TO BE USED BY DIFFERENT HARDWARE ADAPTERS. THE COMBINATION OF THE PIPE AND THE COMMON INTERFACE PROTOCOL ALLOWS MANY DIFFERENT TYPES OF HARDWARE ADAPTERS TO ASYNCHRONOUSLY COMMUNICATE, RESULTING IN HIGHER OVERALL THROUGHOUT DUE TO LOWER INTERRUPT OVERHEAD.(FIG. 5)

公开(公告)号：MY105624A

公开(公告)日：1994-11-30

申请号：MYPI19900776

申请日：1990-05-15

Applicant: IBM

Inventor： ERNEST NELSON MANDESE ,  RICHARD NEIL MENDELSON ,  DHRUVKUMAR M DESAI ,  DOUGLAS RODERICK CHISHOLM ,  FRANCIS MICHAEL BONEVENTO ,  ANDREW BOYCE MCNEIL ,  SAMMY DAVIS DODDS

IPC: G06F13/12

Abstract: A COMMAND INTERFACE INCLUDES PORTS FOR TRANSFERRING INFORMATION BETWEEN A HOST PROCESSOR AND AT LEAST ONE INTELLIGENT SUBSYSTEM WHICH MAY HAVE ATTACHED DEVICES. A COMMAND INTERFACE PORT RECEIVES EITHER A DIRECT COMMAND OR AN INDIRECT COMMAND FROM THE HOST PROCESSOR, WHICH COMMANDS ARE INDICATIVE OF A TYPE OF OPERATION TO BE PERFORMED BY THE ONE SUBSYSTEM OR AN ATTACHED DEVICE. AN ATTENTION PORT RECEIVES A CODE FROM THE HOSE PROCESSOR WHICH IS INDICATIVE OF WHICH ONE OF THE DIRECT COMMAND OR THE INDIRECT COMMAND IS RECEIVED AT THE COMMAND INTERFACE PORT, AND WHICH IS ALSO INDICATIVE OF WHICH OF THE ONE INTELLIGENT SUBSYSTEM OR A DEVICE IS TO EXECUTE THE COMMAND. A COMMAND BUSY/STATUS PORT RECEIVES A CODE FROM THE ONE INTELLIGENT SUBSYSTEM WHICH IS INDICATIVE OF WHETHER OR NOT THE COMMAND INTERFACE PORT AND THE ATTENTION PORT ARE BUSY, AND WHETHER OR NOT THE ONE INTELLIGENT SUBSYSTEM IS ACCEPTING OR REJECTING COMMANDS. THE HOST PROCESSOR CAN READ THIS PORT WITHOUT ALTERING OR UPDATING THE CODE.( FIG 2 )