公开(公告)号：MY107722A

公开(公告)日：1996-05-30

申请号：MYPI19901896

申请日：1990-10-30

Applicant: IBM

Inventor： ROBERT DEAN YODER ,  RUSSELL STEPHEN PADGETT ,  RAFAEL ALVAREZ ,  DEAN ALAN KALMAN ,  SERAFIN JOSE ELEAZAR ,  DOUGLAS RODERICK CHISHOLM

IPC: G06F12/02 ,  G06F13/16 ,  G06F12/06

Abstract: A SELECTED ADDRESS WITHIN ONE OF TWO SEGMENTS OF A MEMORY SPACE (124) OF A SECOND ADDRESS/DATA BUS (116), CAN BE ACCESSED FROM A FIRST BUS (102) THROUGH ONE OF TWO DATA REGISTERS (136 AND 138). IN THE ADDITION, THE LOCATION OF THE TWO SEGMENTS WITHIN THE MEMORY SPACE OF THE SECOND BUS IS SELECTABLE THROUGH TWO SEGMENTS REGISTERS (148 AND150), WHICH ARE ACCESSED FROM THE FIRST BUS THROUGH THE FIRST DATA REGISTER (136). A TWO BYTE WIDE"MODE" REGISTER (126 AND128), WHICH CAN BE DIRECTLY ACCESSED FROM THE FIRST BUS, STORES DATA WITHIN THREE RANGES. WHEN THE MODE REGISTER DATA IS WITHIN THE FIRST RANGE,A SELECTED SEGMENT REGISTER CAN BE ACCESSED THROUGH THE FIRST DATA REGISTER. A FIRST VALUE WITHIN THIS RANGE SELECTS THE FIRST SEGMENT REGISTER (148), WHILE A SECOND VALUE SELECTS THE SECOND SEGMENT REGISTER (150). DATA LOADED INTO THE FIRST AND SECOND SEGMENT REGISTERS POINTS TO FIRST AND SECOND SEGMENTS OF THE SECOND MEMORY SPACE, RESPECTIVELY. WHEN THE MODE REGISTER DATA IS WITHIN THE SECOND RANGE, THIS DATA FUNCTIONS AS A POINTER TO SELECTS AN ADDRESS WITHIN A SELECTED SEGMENT. THE SELECTED ADDRESS IS ACCESSED THROUGH THE DATA REGISTERS; THE FIRST DATA REGISTER (136)ACCESSING THE SELECTED ADDRESS IN THE FIRST SEGMENT, WHILE THE SECOND DATA REGISTER (138) ACCESSES THE SELECTED ADDRESS IN THE SECOND SEGMENT. AFTER A SELECTED ADDRESS HAS BEEN ACCESSED, AN AUTO-INCREMENT CIRCUIT (FIG.2) INCREMENTS THE MODE REGISTER SO THAT THE NEXT SEQUENTIAL ADDRESS IN THE SELECTED SEGMENT CAN BE ACCESSED WITHOUT HAVING TO HAVING TO RELOAD THE MODE REGISTER. WHEN THE MODE REGISTER DATA IS WITHIN THE FIRST RANGE, THE TWO DATA REGISTERS CAN BE DIRECTLY ACCESSED FROM THE FIRST BUS.

公开(公告)号：MY104505A

公开(公告)日：1994-04-30

申请号：MYPI19901890

申请日：1990-10-29

Applicant: IBM

Inventor： ROBERT DEAN YODER ,  SERAFIN JOSE ELEAZAR GARCIA JR ,  RUSSEL STEPHEN PADGETT ,  DOUGLAS RODERICK CHISHOLM ,  DEAN ALAN KALMAN

IPC: G06F13/32 ,  G06F13/362

Abstract: A PLURALITY OF SPECIALIZED CONTROLLERS (E.G., 202, 204& 206), EACH ONE ADAPTED TO CONTROL A PARTICULAR TYPE OF DATA TRANSFER OPERATION, CONTROL THE FLOW OF DATA BETWEEN A SYSTEM BUS (104) AND A LOCAL BUS (106) ON A COMPUTER ADAPTER CARD (102). WHEN THE DIRECT MEMORY ACCESS (DMA) CONTROLLER (202) IS CONTROLLING A DMA OPERATION ON THE LOCAL BUS, CERTAIN OTHER CONTROLLERS (204 & 206) CAN BREAK-IN TO THE CURRENT DMA OPERATION, TEMPORARILY HALTING THE DMA OPERATION UNTIL THE OTHER CONTROLLER HAS COMPLETED ITS DATA TRANSFER OPERATION.TO BREAK IN TO A DMA OPERATION, HANDSHAKING SIGNALS THE DMA CONTROLLER AND THE LOCAL BUS INTERFACE CIRCUIT (212) ARE TEMPORARILY BLOCKED BY BLOCKING SIGNALS FROM A BREAK-IN LOGIC CIRCUIT (210). THE BREAK-IN CIRCUIT INCLUDES A FOUR-STATE MACHINE TO BLOCK THE HANDSHAKING SIGNALS AT THE APPROPRIATE TIMES, AND TO SIGNAL THE INTERRUPTING CONTROLLER TO BEGIN ITS DATA TRANSFER OPERATION. WHEN BREAKING-IN TO A DMA OPERATION IN THIS MANNER, THE OPERATION OF THE DMA CONTROLLER IS NOT ALTERED, INSTEAD, TO THE DMA CONTROLLER, IT APPEARS THAT THE LOCAL BUS INTERFACE CIRCUIT IS MERELY SLOW TO RESPOND WITH ITS ACKNOWLEDGE HANDSHAKE.(FIG. 2)

公开(公告)号：MY105624A

公开(公告)日：1994-11-30

申请号：MYPI19900776

申请日：1990-05-15

Applicant: IBM

Inventor： ERNEST NELSON MANDESE ,  RICHARD NEIL MENDELSON ,  DHRUVKUMAR M DESAI ,  DOUGLAS RODERICK CHISHOLM ,  FRANCIS MICHAEL BONEVENTO ,  ANDREW BOYCE MCNEIL ,  SAMMY DAVIS DODDS

IPC: G06F13/12

Abstract: A COMMAND INTERFACE INCLUDES PORTS FOR TRANSFERRING INFORMATION BETWEEN A HOST PROCESSOR AND AT LEAST ONE INTELLIGENT SUBSYSTEM WHICH MAY HAVE ATTACHED DEVICES. A COMMAND INTERFACE PORT RECEIVES EITHER A DIRECT COMMAND OR AN INDIRECT COMMAND FROM THE HOST PROCESSOR, WHICH COMMANDS ARE INDICATIVE OF A TYPE OF OPERATION TO BE PERFORMED BY THE ONE SUBSYSTEM OR AN ATTACHED DEVICE. AN ATTENTION PORT RECEIVES A CODE FROM THE HOSE PROCESSOR WHICH IS INDICATIVE OF WHICH ONE OF THE DIRECT COMMAND OR THE INDIRECT COMMAND IS RECEIVED AT THE COMMAND INTERFACE PORT, AND WHICH IS ALSO INDICATIVE OF WHICH OF THE ONE INTELLIGENT SUBSYSTEM OR A DEVICE IS TO EXECUTE THE COMMAND. A COMMAND BUSY/STATUS PORT RECEIVES A CODE FROM THE ONE INTELLIGENT SUBSYSTEM WHICH IS INDICATIVE OF WHETHER OR NOT THE COMMAND INTERFACE PORT AND THE ATTENTION PORT ARE BUSY, AND WHETHER OR NOT THE ONE INTELLIGENT SUBSYSTEM IS ACCEPTING OR REJECTING COMMANDS. THE HOST PROCESSOR CAN READ THIS PORT WITHOUT ALTERING OR UPDATING THE CODE.( FIG 2 )