公开(公告)号：US3675133A

公开(公告)日：1972-07-04

申请号：US3675133D

申请日：1971-06-21

Applicant: IBM

Inventor： FRANKENY RICHARD F ,  TUTTLE JOEY K

IPC: H03K5/05 ,  H03K5/06 ,  H04L25/04 ,  H03K5/159 ,  H03K17/26

CPC classification number: H03K5/06 ,  H03K5/05

Abstract: Input data comprises a plurality of serial random-width pulses each having a leading and a trailing edge. The relative position of each leading and trailing edge is independently adjustable in accordance with external data to give output data comprising a plurality of serial pulses derived from, but selectively different than, the input data. A data clock generates a transition signal for each pulse edge. Each transition signal is directed into a different variable delay circuit which imposes a delay dictated by external data. The delayed transitions operate a pulse regenerating flip-flop to form the output data. Appropriate gating controls permit width control of only selected pulses. By defining normal data as delayed input data, output data may be shifted either forward or backward in time relative to the normal data.

Abstract translation: 输入数据包括多个具有前沿和后沿的串行随机宽度脉冲。 每个前沿和后沿的相对位置可以根据外部数据独立地进行调整，以给出包括从输入数据导出但是有选择地不同的多个串行脉冲的输出数据。 数据时钟产生每个脉冲沿的转换信号。 每个转换信号被引导到不同的可变延迟电路，该电路施加由外部数据指示的延迟。 延迟转换操作脉冲再生触发器以形成输出数据。 适当的门控控制允许仅选择脉冲的宽度控制。 通过将正常数据定义为延迟的输入数据，输出数据可以相对于正常数据在时间上向前或向后偏移。

公开(公告)号：JPH11316737A

公开(公告)日：1999-11-16

申请号：JP2404499

申请日：1999-02-01

Applicant: IBM

Inventor： BEERS GREGORY E ,  FRANKENY RICHARD F ,  MIZUKARU MODDO SUMADI

IPC: G06F13/36 ,  G06F13/40 ,  H03M5/16

Abstract: PROBLEM TO BE SOLVED: To use data with parallel data buses of defined width together with a circuit which transmits and receives by providing plural inputs which receive a 1st set of parallel data and >=1 outputs which transmit a 2nd set of parallel data signals, making the 2nd set smaller than the 1st set and making the 2nd set include a width reduction circuit element that represents information included in the 1st set. SOLUTION: A processing circuit element 100 sends its output to a width reduction circuit element 102 through processing element/width reduction input lines 104. The element 102 receives N×M (N is an integer of >=1 and M is an integer of >=2) pieces of the lines 104 as inputs and encodes information included in N×M pieces of the lines 104 into N pieces of output lines 106. N pieces of the lines 106 are connected to a parallel connector 108 which is adapted so as to be easily connected to a parallel data bus 110 consisting of N pieces of data bus lines 112. Thus, the transmission speed of the bus 110 is equivalently accelerated to M times.

公开(公告)号：SG44062A1

公开(公告)日：1997-11-14

申请号：SG1996011155

申请日：1996-11-15

Applicant: IBM

Inventor： FRANKENY RICHARD F

IPC: H01L23/498 ,  H01L25/065 ,  H05K7/02 ,  H01L23/52

Abstract: A multiple chip module architecture capable of forming structures having selectable aspect ratios which themselves form the basis for higher levels of integration in analogous manner. The modular architecture uses a flexible interconnect of patterned copper on polymer to successively reorient the connection plane between successive levels, permitting the selective stacking of module levels to create the desired aspect ratio of the multiple chip module. Interconnection between levels may be accomplished by solder reflow, direct dendritic bonding, or connection through a dendritic interposer.

公开(公告)号：CA1155911A

公开(公告)日：1983-10-25

申请号：CA353784

申请日：1980-06-11

Applicant: IBM

Inventor： CLANCY DOUGLAS E ,  FRANKENY RICHARD F ,  OLSON GEORGE P

IPC: H02P8/12 ,  H02P8/32 ,  H02P25/08 ,  H02K37/00 ,  G05B19/40

Abstract: ELECTRONIC DAMPING OF STEPPER MOTOR A damping control system for a three phase stepper motor. A reluctance velocity transducer is used for each of the three phases. The output of each of the transducers is proportional to the rotational velocity of the motor. Each of the transducers is rotationally phase shifted 3.75 with respect to one another and phased to the motor rotor rotationally such that the zero voltage crossings of the transducers correspond to the zero torque crossings of the motor. During damping or detenting of the motor the selected phase has current applied to it which is equal to a predetermined fixed value plus the feedback from its associated transducer. The windings on each side of the detent position have current applied to them which is proportional to the voltage from their respective feedback transducers. The voltage in each of the windings is amplified by a selected gain constant. The current in each of the windings is such that maximum torque is applied to drive the motor to the detent position with appropriate current reversals in the windings to damp out any kinetic energy in the rotor during detenting. AT9-78-032

公开(公告)号：HK1000900A1

公开(公告)日：2002-03-22

申请号：HK97102537

申请日：1997-12-20

Applicant: IBM

Inventor： FRANKENY RICHARD F

IPC: H01L23/498 ,  H01L25/065 ,  H05K7/02 ,  H01L ,  G11C

Abstract: A multiple chip module architecture capable of forming structures having selectable aspect ratios which themselves form the basis for higher levels of integration in analogous manner. The modular architecture uses a flexible interconnect of patterned copper on polymer to successively reorient the connection plane between successive levels, permitting the selective stacking of module levels to create the desired aspect ratio of the multiple chip module. Interconnection between levels may be accomplished by solder reflow, direct dendritic bonding, or connection through a dendritic interposer.

公开(公告)号：PL181152B1

公开(公告)日：2001-06-29

申请号：PL32132496

申请日：1996-01-19

Applicant: IBM

Inventor： BEERS GREGORY E ,  FRANKENY RICHARD F ,  SMADI MITHKAL M

IPC: G06F3/00 ,  H04L5/14 ,  H04L25/02 ,  H03K19/00 ,  H04B3/02

Abstract: A method and apparatus are disclosed for sending and receiving logic signals. A driver is connected to a first end of a transmission line with a predetermined impedance and first and second transmission line ends for communicating the logic signals. The driver has a source for sending the logic signals, and a reference generator connected to the source for setting the magnitude of the signals sent by the source. A receiver is connected to the second transmission line end, and has a transmission line terminator for sinking the signals, and a reference generator connected to the terminator for setting a bias of the terminator to establish a certain family of terminator impedances for sinking the signals. The driver reference generator and the receiver reference generator interactively match the terminator impedance to the transmission line for the set magnitude of the signals.