公开(公告)号：JPH11316737A

公开(公告)日：1999-11-16

申请号：JP2404499

申请日：1999-02-01

Applicant: IBM

Inventor： BEERS GREGORY E ,  FRANKENY RICHARD F ,  MIZUKARU MODDO SUMADI

IPC: G06F13/36 ,  G06F13/40 ,  H03M5/16

Abstract: PROBLEM TO BE SOLVED: To use data with parallel data buses of defined width together with a circuit which transmits and receives by providing plural inputs which receive a 1st set of parallel data and >=1 outputs which transmit a 2nd set of parallel data signals, making the 2nd set smaller than the 1st set and making the 2nd set include a width reduction circuit element that represents information included in the 1st set. SOLUTION: A processing circuit element 100 sends its output to a width reduction circuit element 102 through processing element/width reduction input lines 104. The element 102 receives N×M (N is an integer of >=1 and M is an integer of >=2) pieces of the lines 104 as inputs and encodes information included in N×M pieces of the lines 104 into N pieces of output lines 106. N pieces of the lines 106 are connected to a parallel connector 108 which is adapted so as to be easily connected to a parallel data bus 110 consisting of N pieces of data bus lines 112. Thus, the transmission speed of the bus 110 is equivalently accelerated to M times.