公开(公告)号：IT1160420B

公开(公告)日：1987-03-11

申请号：IT2265680

申请日：1980-06-09

Applicant: IBM

Inventor： DINWIDDIE JOHN MONROE ,  FREEMAN BODDY JOE ,  JACKSON TIMOTHY ,  ZIPOY WILLIAM LEWIS

IPC: G06F20060101 ,  G06F

Abstract: The input/output controller includes a microprocessor for supervising data transfer between a host processor and the controller and a microprocessor I/O bus coupled to I/O units. A storage unit is located in the I/O controller for providing a data transfer interface between the microprocessor I/O bus and the I/O channel bus of the host processor. First storage accessing circuitry including the microprocessor and chip select decoder provides a data transfer path between a dual-port random access storage mechanism and an I/O unit. Second storage accessing circuitry including a direct memory access controller unit and chip select decoder supplies host processor main storage addresses to the host processor and controller storage addresses to the storage mechanism. These addresses enable transfer of data between the host processor main storage unit and the controller storage mechanism in a first data transfer mode e.g. a cycle steal mode.. More efficient and flexible data transfer are achieved where several I/O units are connected to the I/O controller. So that a high performance I/O controller is provided which is flexible and versatile in terms of the kinds and numbers of tasks it can perform and I/O units it can handle.