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    PRINTER CONTROL DEVICE
    1.
    发明专利
    PRINTER CONTROL DEVICE 未知

    公开(公告)号：DE3068016D1

    公开(公告)日：1984-07-05

    申请号：DE3068016

    申请日：1980-06-24

    Applicant: IBM

    Inventor： JACKSON TIMOTHY ,  MALKEMES CHARLES DAVID ,  ZIPOY WILLIAM LEWIS

    IPC: B41J2/51 ,  B41J19/18 ,  G06K15/00 ,  G06K15/08 ,  G06K15/10 ,  G06F3/12

    Abstract: There is disclosed herein printer control logic for controlling a matrix printer. The control logic includes an interruptable microprocessor, together with associated memory. Additionally the control logic includes a programmable timer which provides a signal a determined time after being programmed. The control logic responds to print emitter signals manifesting an incremental movement of the print head by interrupting the microprocessor. The microprocessor then programs the timer to provide signals after a programmed delay time to again interrupt the microprocessor. The microprocessor then provides signals causing the operation of the print elements on print head.

    PRINTER CONTROL LOGIC
    2.
    发明专利
    PRINTER CONTROL LOGIC 未知

    公开(公告)号：CA1128364A

    公开(公告)日：1982-07-27

    申请号：CA353162

    申请日：1980-06-02

    Applicant: IBM

    Inventor： JACKSON TIMOTHY ,  MALKEMES CHARLES D ,  ZIPOY WILLIAM L

    IPC: B41J2/51 ,  B41J19/18 ,  G06K15/00 ,  G06K15/08 ,  G06K15/10 ,  B41J3/12

    Abstract: There is disclosed herein printer control logic for controlling a matrix printer. The control logic includes an interruptable microprocessor, together with associated memory. Additionally the control logic includes a programmable timer which provides a signal a determined time after being programmed. The control logic responds to print emitter signals manifesting an incremental movement of the print head by interrupting the microprocessor. The microprocessor then programs the timer to provide signals after a programmed delay time to again interrupt the microprocessor. The microprocessor then provides signals causing the operation of the print elements on print head. BC9-79-024

    HIGH PERFORMANCE I/O CONTROLLER FOR TRANSFERRING DATA BETWEEN A HOST PROCESSOR AND MULTIPLE I/O UNITS
    5.
    发明专利
    HIGH PERFORMANCE I/O CONTROLLER FOR TRANSFERRING DATA BETWEEN A HOST PROCESSOR AND MULTIPLE I/O UNITS 未知

    公开(公告)号：CA1148265A

    公开(公告)日：1983-06-14

    申请号：CA352373

    申请日：1980-05-21

    Applicant: IBM

    Inventor： DINWIDDIE JOHN M JR ,  FREEMAN BOBBY J ,  JACKSON TIMOTHY ,  ZIPOY WILLIAM L

    IPC: G06F13/28 ,  G06F3/00 ,  G06F3/06 ,  G06F9/22 ,  G06F9/26 ,  G06F9/46 ,  G06F11/34 ,  G06F13/00

    Abstract: HIGH PERFORMANCE I/O CONTROLLER FOR TRANSFERRING DATA BETWEEN A HOST PROCESSOR AND MULTIPLE I/O UNITS An I/O controller for transferring data between a host processor and an I/O unit is disclosed comprising: a random access storage unit located in the I/O controller for storing data; first selectively operable data transfer circuitry for providing a data transfer path between the host processor and the controller storage unit; second selectively operable data transfer circuitry for providing a data transfer path between the controller storage unit and the I/O unit; first storage accessing circuitry for supplying addresses to the controller storage unit and selection signals to the second data transfer circuitry for enabling the transfer of data between the controller storage unit and the I/O unit; second storage accessing circuitry for supplying host processor main storage addresses to the host processor, controller storage addresses to the controller storage unit and selection signals to the first data transfer circuitry for enabling the transfer of data between the host processor main storage unit and the controller storage unit in a first data transfer mode; third storage accessing circuitry responsive to addresses received from the host processor for supplying addresses to the controller storage unit and selection signals to the first data transfer circuitry for enabling the transfer of data between the host processor and the controller storage unit in a second data transfer mode; and interleaving control circuitry for enabling the second mode data transfers to be interleaved with the first mode data transfers.

    6.
    发明专利
    未知

    公开(公告)号：IT1149980B

    公开(公告)日：1986-12-10

    申请号：IT2295180

    申请日：1980-06-23

    Applicant: IBM

    Inventor： JACKSON TIMOTHY ,  MALKEMES CHARLES DAVID ,  ZIPOY WILLIAM LEWIS

    IPC: B41J2/51 ,  B41J19/18 ,  G06K15/00 ,  G06K15/08 ,  G06K15/10 ,  H05K

    Abstract: There is disclosed herein printer control logic for controlling a matrix printer. The control logic includes an interruptable microprocessor, together with associated memory. Additionally the control logic includes a programmable timer which provides a signal a determined time after being programmed. The control logic responds to print emitter signals manifesting an incremental movement of the print head by interrupting the microprocessor. The microprocessor then programs the timer to provide signals after a programmed delay time to again interrupt the microprocessor. The microprocessor then provides signals causing the operation of the print elements on print head.

    High-performance input-output controller
    7.
    发明专利
    High-performance input-output controller 未知

    公开(公告)号：IT1160420B

    公开(公告)日：1987-03-11

    申请号：IT2265680

    申请日：1980-06-09

    Applicant: IBM

    Inventor： DINWIDDIE JOHN MONROE ,  FREEMAN BODDY JOE ,  JACKSON TIMOTHY ,  ZIPOY WILLIAM LEWIS

    IPC: G06F20060101 ,  G06F

    Abstract: The input/output controller includes a microprocessor for supervising data transfer between a host processor and the controller and a microprocessor I/O bus coupled to I/O units. A storage unit is located in the I/O controller for providing a data transfer interface between the microprocessor I/O bus and the I/O channel bus of the host processor. First storage accessing circuitry including the microprocessor and chip select decoder provides a data transfer path between a dual-port random access storage mechanism and an I/O unit. Second storage accessing circuitry including a direct memory access controller unit and chip select decoder supplies host processor main storage addresses to the host processor and controller storage addresses to the storage mechanism. These addresses enable transfer of data between the host processor main storage unit and the controller storage mechanism in a first data transfer mode e.g. a cycle steal mode.. More efficient and flexible data transfer are achieved where several I/O units are connected to the I/O controller. So that a high performance I/O controller is provided which is flexible and versatile in terms of the kinds and numbers of tasks it can perform and I/O units it can handle.

    CONTROL LOGIC FOR WIRE MATRIX PRINTER
    8.
    发明专利
    CONTROL LOGIC FOR WIRE MATRIX PRINTER 未知

    公开(公告)号：AU529183B2

    公开(公告)日：1983-05-26

    申请号：AU5948480

    申请日：1980-06-20

    Applicant: IBM

    Inventor： JACKSON TIMOTHY ,  MALKEMES CHARLES DAVID ,  ZIPOY WILLIAM LEWIS

    IPC: B41J2/51 ,  B41J19/18 ,  G06K15/00 ,  G06K15/08 ,  G06K15/10 ,  B41J3/12 ,  B41J7/84

    Abstract: There is disclosed herein printer control logic for controlling a matrix printer. The control logic includes an interruptable microprocessor, together with associated memory. Additionally the control logic includes a programmable timer which provides a signal a determined time after being programmed. The control logic responds to print emitter signals manifesting an incremental movement of the print head by interrupting the microprocessor. The microprocessor then programs the timer to provide signals after a programmed delay time to again interrupt the microprocessor. The microprocessor then provides signals causing the operation of the print elements on print head.

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