公开(公告)号：CA1058325A

公开(公告)日：1979-07-10

申请号：CA254113

申请日：1976-06-04

Applicant: IBM

Inventor： FREEMAN LEO B ,  INCERTO ROBERT J ,  PETROSKY JOSEPH A JR

IPC: G11C11/412 ,  H01L21/8236 ,  H01L27/088 ,  H01L29/78 ,  H03K3/356 ,  H03K17/00 ,  H03K17/041 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0944 ,  H03K19/21 ,  H03K19/08 ,  G11C11/40

Abstract: ENHANCEMENT-AND DEPLETION-TYPE FIELD EFFECT TRANSISTORS CONNECTED IN PARALLEL A circuit comprising the parallel connection of an enhancement-and a depletion-type FET which exhibits reduced power and improved performance for both logic as well as memory circuits. Cross-coupled enhancement-type field effect transistors and first and second sets of field effect transistors connect the internal switching nodes of the cross-coupled transistors to bit-sense lines. The first and second sets of field effect transistors each comprise a depletion-type field effect transistor and an enhancementtype field effect transistor connected in parallel.

公开(公告)号：FR2313819A1

公开(公告)日：1976-12-31

申请号：FR7613464

申请日：1976-04-29

Applicant: IBM

Inventor： FREEMAN LEO B ,  INCERTO ROBERT J ,  PETROSKY JOSEPH A JR

IPC: G11C11/412 ,  H01L21/8236 ,  H01L27/088 ,  H01L29/78 ,  H03K3/356 ,  H03K17/00 ,  H03K17/041 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0944 ,  H03K19/21 ,  H03K19/08 ,  G11C11/40

Abstract: A circuit comprising the parallel connection of an enhancement-and a depletion-type FET which exhibits reduced power and improved performance for both logic as well as memory circuits.