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    Apparatus and method for rate detection
    1.
    发明授权
    Apparatus and method for rate detection 失效
    用于速率检测的装置和方法

    公开(公告)号：US3596065A

    公开(公告)日：1971-07-27

    申请号：US3596065D

    申请日：1968-11-07

    Applicant: IBM

    Inventor： LAZARCHICK NICHOLAS JR ,  FREY ALEXANDER H JR ,  SCHROEDER EUGENE N

    IPC: G06F17/18 ,  G06J1/00 ,  H03K23/02

    CPC classification number: G06J1/00 ,  G06F17/18

    Abstract: A method and apparatus for rate detection of the ratio of first events to second events in a stream of basic events where each event in the stream of basic events must either be a first event or second event. The method provides an indication of the average of the quantized log to the base two of the number of first events that occurs between the occurrence of second events. The apparatus comprises a binary counter, a shift register, a digital to analog converter alarm and metering logic.

    Method and apparatus for triple error correction
    2.
    发明授权
    Method and apparatus for triple error correction 失效
    三重误差校正的方法和装置

    公开(公告)号：US3622982A

    公开(公告)日：1971-11-23

    申请号：US3622982D

    申请日：1969-02-28

    Applicant: IBM

    Inventor： CLARK BRADFORD S JR ,  FREY ALEXANDER H JR

    IPC: H03M13/15 ,  H04L1/10

    CPC classification number: H03M13/15

    Abstract: The invention relates to a simplified method for extracting triple error correction information from a (23, 12) BoseChaudhuri code which is the Golay code. In a 23-bit word having three or less errors, the method provides correction on a bit-bybit basis. Each bit is assumed to be in error and corrected, the remaining 22 bits are then interrogated for two or less errors. Also disclosed is the apparatus for extracting the error correction information from the Golay code in a Bose-Chaudhuri code is comprised of a check word generator and shifting means, decoder circuitry, false error indication inhibit circuitry, control circuitry and error action circuitry.

    Apparatus and method for obtaining synchronization of a maximum length pseudorandom sequence
    4.
    发明授权
    Apparatus and method for obtaining synchronization of a maximum length pseudorandom sequence 失效
    获得最大长度序列同步化的装置和方法

    公开(公告)号：US3648237A

    公开(公告)日：1972-03-07

    申请号：US3648237D

    申请日：1969-02-28

    Applicant: IBM

    Inventor： FREY ALEXANDER H JR ,  SCHLOSBURG BURTON E ,  TYGIELSKI RALPH E

    IPC: G06F11/18 ,  H03K5/00 ,  H04L7/00 ,  H04L7/04 ,  H04L7/08

    CPC classification number: H04L7/043

    Abstract: An apparatus and method for obtaining synchronization of a maximum length pseudorandom sequence included within input data. The apparatus comprises means for generating a predicted pseudorandom sequence, means for comparing the pseudorandom sequence with the input data and means for determining from said comparison whether said predicted pseudorandom sequence and said input data are the same. The method employed is a bit-by-bit comparison between the predicted values of a predicted pseudorandom sequence and the incoming values of the input data, synchronization is indicated when a predetermined number of successive comparisons are obtained, where said predetermined number of successive comparisons is less in number than the maximum length of the specified maximum length pseudorandom sequence.

    Abstract translation: 一种用于获得包括在输入数据内的最大长度伪随机序列的同步的装置和方法。 该装置包括用于产生预测伪随机序列的装置，用于将伪随机序列与输入数据进行比较的装置，以及用于根据所述比较确定所述预测伪随机序列和所述输入数据是否相同的装置。 所采用的方法是在预测的伪随机序列的预测值和输入数据的输入值之间进行逐位比较，当获得预定数量的连续比较时指示同步，其中所述预定数量的连续比较是 数量少于规定的最大长度伪随机序列的最大长度。

    Data Transmission System
    10.
    发明专利
    Data Transmission System 未知

    公开(公告)号：GB1198510A

    公开(公告)日：1970-07-15

    申请号：GB5695067

    申请日：1967-12-13

    Applicant: IBM

    Inventor： FREY ALEXANDER H JR

    IPC: H03M13/17 ,  H04L1/00

    Abstract: 1,198,510. Polynomial error-correcting codes. INTERNATIONAL BUSINESS MACHINES CORP. 13 Dec., 1967 [15 Dec., 1966], No. 56950/67. Heading G4A. In a data transmission system a message consists of information digits and remainder digits obtained by dividing them by an errorcorrection coding polynomial, receiving means multiplying a received message by X a where a = p - (n-r) where p is the period of the coding polynomial, i.e. the smallest positive integer for which Xp - 1 is divisible by the coding polynomial, n is the number of digits in the message and r is the degree of the coding polynomial, and dividing by the coding polynomial to provide a remainder indicating any errors in the message. In one embodiment, the transmitter includes a linear-feedback shift register (with modulo-two addition) to obtain the remainder digits (bits) for the message, the information bits being effectively multiplied by Xr before division. Fig. 3 shows the receiver, including a linear-feedback shift register 39 (with modulo-two addition), feedback from its output (stage 100) being via AND 66, there also being feedforward from the input (top left) as shown, to accomplish the multiplication and division in one operation. The information bits (or the whole message) are also entered into buffer storage 52. When the remainder from the multiplication and division has been produced in the shift register 39, the contents of the buffer storage 52 are passed to the output 64 via modulo-two adder 62, in synchronism with shifting (with feedback) of shift register 39. Detection of all-zeros in the first (r - b) stages of shift register 39 (where b is the maximum length of a correctable burst of errors) by AND 54 causes the other bits in the shift register 39 to correct the corresponding bits from the buffer storage 52 at modulo-two adder 62 via AND 58, the feedback being disabled using inverter 68. As shown, n = 200 (100 information bits and 100 check bits), r=100, b=90. Portions of the shift registers may be replaced by delay lines. The buffer storage may be a shift register, delay line, or magnetic tape or core memory. A second shift register, similar to 39 but without the feedforward from the input mentioned, could be provided to control the correction, being fed from register 39 after the multiplication and division to allow register 39 to proceed with the next message. A second embodiment comprises a feedback shift register used for transmitter division and receiver multiplication and division alternately in interleaved fashion, intermediate results being held temporarily in a main store (magnetic disc, drum or cores) and a second feedback shift register being provided to control correction as above. Application to telephone and magnetic tape systems is mentioned.

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