公开(公告)号：EP0732701A3

公开(公告)日：1998-11-25

申请号：EP96480016

申请日：1996-02-06

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  WATANABE YOHJI ,  FUJII SHUSO

IPC: G11C11/409 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/04

CPC classification number: G11C11/4094

Abstract: A fault-tolerant DRAM design minimizes current flow in the event of a cross-fail. A bit-line precharge current limiter is provided for the bit-line precharge equalizer circuit. The bit-line precharge current limiter is both simple and effective, requiring very little silicon area to implement. The current limiter provides self current-limiting for defective bit-lines, without the necessity for a reference cell.

Abstract translation: 容错DRAM设计可以在发生交叉故障时最大限度地减少电流。 为位线预充电均衡器电路提供位线预充电电流限制器。 位线预充电电流限制器既简单又有效，需要很少的硅面积来实现。 电流限制器为有缺陷的位线提供自限流，而不需要参考单元。

公开(公告)号：DE69614905T2

公开(公告)日：2002-04-04

申请号：DE69614905

申请日：1996-02-06

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  WATANABE YOHJI ,  FUJII SHUSO

IPC: G11C11/409 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/04

Abstract: The memory comprises several word-lines and complementary bit-line pairs. A source of precharge voltage for precharges the complementary bit-line pairs. Several precharge equalisation circuits each of which comprises three field effect transistors. The one FET is connected across a corresponding complementary pair of bit-lines and the other two FET's are connected in series with a respective complementary pair of bit-lines. The gates of each of the FET's are connected to receive a precharge equalisation control signal. The precharge equalisation circuits is connected to the source of the precharge voltage. One precharge equalisation circuit precharges each of the complementary bit-line pairs. A current limiter limits the precharge current flowing into the complementary bit-line pairs to a precharge current limit value. The current limiter comprises a FET which is biased to limit current flow through the transistors to the precharge current limit value.

公开(公告)号：DE69614905D1

公开(公告)日：2001-10-11

申请号：DE69614905

申请日：1996-02-06

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  WATANABE YOHJI ,  FUJII SHUSO

IPC: G11C11/409 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/04

Abstract: The memory comprises several word-lines and complementary bit-line pairs. A source of precharge voltage for precharges the complementary bit-line pairs. Several precharge equalisation circuits each of which comprises three field effect transistors. The one FET is connected across a corresponding complementary pair of bit-lines and the other two FET's are connected in series with a respective complementary pair of bit-lines. The gates of each of the FET's are connected to receive a precharge equalisation control signal. The precharge equalisation circuits is connected to the source of the precharge voltage. One precharge equalisation circuit precharges each of the complementary bit-line pairs. A current limiter limits the precharge current flowing into the complementary bit-line pairs to a precharge current limit value. The current limiter comprises a FET which is biased to limit current flow through the transistors to the precharge current limit value.