公开(公告)号：CA2026768C

公开(公告)日：1996-07-23

申请号：CA2026768

申请日：1990-10-02

Applicant: IBM

Inventor： PADGETT RUSSELL S ,  CHISHOLM DOUGLAS R ,  GARCIA SERAFIN J E JR ,  ALVAREZ RAFAEL ,  KALMAN DEAN A ,  YODER ROBERT D

IPC: G06F12/06 ,  G06F12/02 ,  G06F13/16

Abstract: A selected address within one of two segments of a memory space of a second address/data bus, can be accessed from a first bus through one of two data registers. In addition, the location of the two segments within the memory space of the second bus is selectable through two segment registers, which are accessed from the first bus through the first data register. A two byte wide "mode" register, which can be directly accessed from the first bus, stores data within three ranges. When the mode register data is within the first range, a selected segment register can be accessed through the first data register. A first value within this range selects the first segment register, while a second value selects the second segment register. Data loaded into the first and second segment registers points to first and second segments of the second memory space, respectively. When the mode register data is within the second range, this data functions as a pointer to select an address within a selected segment. The selected address is accessed through the data registers; the first data register accessing the selected address in the first segment, while the second data register accesses the selected address in the second segment. After a selected address has been accessed, an auto-increment circuit increments the mode register so that the next sequential address in the selected segment can be accessed without having to reload the mode register. When the mode register data is within the first range, the two data registers can be directly accessed from the first bus.

公开(公告)号：CA2026737C

公开(公告)日：1996-01-23

申请号：CA2026737

申请日：1990-10-02

Applicant: IBM

Inventor： GARCIA SERAFIN J E JR ,  CHISHOLM DOUGLAS R ,  KALMAN DEAN A ,  PADGETT RUSSELL S ,  YODER ROBERT D

IPC: G06F13/32 ,  G06F13/362 ,  G06F13/24

Abstract: A plurality of specialized controllers, each one adapted to control a particular type of data transfer operation, control the flow of data between a system bus and a local bus on a computer adapter card. When the Direct Memory Access (DMA) controller is controlling a DMA operation on the local bus, certain other controllers can break-in to the current DMA operation, temporarily halting the DMA operation until the other controller has completed its data transfer operation. To break-in to a DMA operation, handshaking signals between the DMA controller and the local bus interface circuit are temporarily blocked by blocking signals from a break-in logic circuit. The break-in circuit includes a four-state state machine to block the handshaking signals at the appropriate times, and to signal the interrupting controller to begin its data transfer operation. When breaking-in to a DMA operation in this manner, the operation of the DMA controller is not altered; instead, to the DMA controller, it appears that the local bus interface circuit is merely slow to respond with its acknowledge handshake.

公开(公告)号：CA2026768A1

公开(公告)日：1991-05-14

申请号：CA2026768

申请日：1990-10-02

Applicant: IBM

Inventor： PADGETT RUSSELL S ,  CHISHOLM DOUGLAS R ,  GARCIA SERAFIN J E JR ,  ALVAREZ RAFAEL ,  KALMAN DEAN A ,  YODER ROBERT D

IPC: G06F12/06 ,  G06F12/02 ,  G06F13/16

Abstract: A selected address within one of two segments of a memory space (124) of a second address/data bus (116), can be accessed from a first bus (102) through one of two data registers (136 and 138). In addition, the location of the two segments within the memory space of the second bus is selectable through two segment registers (148 and 150), which are accessed from the first bus through the first data register (136). A two byte wide "mode" register (126 and 128), which can be directly accessed from the first bus, stores data within three ranges. When the mode register data is within the first range, a selected segment register can be accessed through the first data register. A first value within this range selects the first segment register (148), while a second value selects the second segment register (150). Data loaded into the first and second segment registers points to first and second segments of the second memory space, respectively. When the mode register data is within the second range, this data functions as a pointer to select an address within a selected segment. The selected address is accessed through the data registers; the first data register (136) accessing the selected address in the first segment, while the second data register (138) accesses the selected address in the second segment. After a selected address has been accessed, an auto-increment circuit increments the mode register so that the next sequential address in the selected segment can be accessed without having to reload the mode register. When the mode register data is within the third range, the two data registers can be directly accessed from the first bus.

公开(公告)号：CA2026737A1

公开(公告)日：1991-05-14

申请号：CA2026737

申请日：1990-10-02

Applicant: IBM

Inventor： GARCIA SERAFIN J E JR ,  CHISHOLM DOUGLAS R ,  KALMAN DEAN A ,  PADGETT RUSSELL S ,  YODER ROBERT D

IPC: G06F13/32 ,  G06F13/362

Abstract: A plurality of specialized controllers, e.g. 202, 204 & 206, each one adapted to control a particular type of data transfer operation, control the flow of data between a system bus 104 and a local bus 106 on a computer adapter card 102. When the Direct Memory Access DMA controller 202 is controlling a DMA operation on the local bus, certain other controllers 204 & 206 can break-in to the current DMA operation, temporarily halting the DMA operation until the other controller has completed its data transfer operation. To break-in to a DMA operation, handshaking signals between the DMA controller and the local bus interface circuit 212 are temporarily blocked by blocking signals from a break-in logic circuit 210 . The break-in circuit includes a four-state state machine to block the handshaking signals at the appropriate times, and to signal the interrupting controller to begin its data transfer operation. When breaking-in to a DMA operation in this manner, the operation of the DMA controller is not altered; instead, to the DMA controller, it appears that the local bus interface circuit is merely slow to respond with its acknowledge handshake.