公开(公告)号：CA2012400A1

公开(公告)日：1990-12-09

申请号：CA2012400

申请日：1990-03-16

Applicant: IBM

Inventor： BONEVENTO FRANCIS M ,  CHISHOLM DOUGLAS R ,  DODDS SAMMY D ,  DESAI DHRUVKUMAR M ,  MANDESE ERNEST N ,  MCNEILL ANDREW B ,  MENDELSON RICHARD N

IPC: G06F13/12

Abstract: A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

公开(公告)号：BR9002710A

公开(公告)日：1991-08-20

申请号：BR9002710

申请日：1990-06-08

Applicant: IBM

Inventor： BONEVENTO FRANCIS M ,  CHISHOLM DOUGLAS R ,  DODDS SAMMY D ,  DESAI DHRUVKUMAR M ,  MANDESE ERNEST N ,  MCNEILL ANDREW B ,  MENDELSON RICHARD N

IPC: G06F13/12 ,  G06F15/20 ,  G06F13/00

Abstract: A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

公开(公告)号：CA1118529A

公开(公告)日：1982-02-16

申请号：CA324854

申请日：1979-04-04

Applicant: IBM

Inventor： BROWN LEWIS W ,  CHISHOLM DOUGLAS R ,  DIXON JERRY D

IPC: G06F13/12 ,  G06F13/32 ,  G06F3/04

Abstract: A data processor input/output controller which is particularly useful as a microcontroller for the transfer of data between a host processor and one or more peripheral input/output devices in a digital data processing system. This input/output (I/O) controller is a subchannel controller for offloading a goodly portion of the subchannel control function from the host processor. This I/O controller includes a microprocessor for assisting and supervising the controller internal operations. Also included in the controller is an automatic high-speed data bypass mechanism whereby data may be transferred from the host processor to the I/O device or vice versa without having to pass through the microprocessor and without requiring any intervention on the part of the microprocessor during such automatic transfer. Provision is made for enabling the microprocessor to perform other functions, such as the presentation of interrupts to the host processor and the servicing of additional I/O commands from the host processor concurrently with the transfer of data via the automatic bypass mechanism. This capability is particularly useful where two or more I/O devices are connected to the controller. The automatic bypass mechanism is constructed to communicate with the host processor in a cycle steal mode. A look-ahead mechanism is provided for more quickly issuing the cycle steal requests to the host processor when operating in the automatic bypass mode. BC9-78-004

公开(公告)号：CO4700362A1

公开(公告)日：1998-12-29

申请号：CO92323128

申请日：1990-06-01

Applicant: IBM

Inventor： BONEVENTO FRANCIS M ,  CHISHOLM DOUGLAS R ,  SAMMY D DODDS ,  DHRUVKUMAR M DESAI ,  MANDESE ERNEST N ,  MC NEILL ANDREW B ,  MENDELSON RICHARD N

IPC: G06F13/00 ,  G06F13/12

Abstract: En un sistema procesador de datos que incluye un sistemacentral, y al menos un subsistema que puede llevar dispositivos unidos a él, la combinación que comprende: una interfase de órdenes para transferir información entre el sistema central y dicho un subsistema, incluyendo dicha interfase de órdenes: una primera puerta para recibir una orden directa o una orden indirecta desde dicho sistema central, las cuales órdenes son indicativas del tipo de operación que ha de realizarse en dicho subsistema o en los dispositivos unidos a él; y una segunda puerta para recibir desde dicho sistema central un código indicativo de cual dichas ordenes directa o indirecta se recibe en dicha primera puerta, y siendo también indicativo de cual de dicho un subsistema o de un dispositivo unido a él, ha de ejecutar la orden recibida en dicha primera puerta". En un sistema computador que incluye un procesador central que tiene una memoria del sistema, y al menos un subsistema inteligente que puede tener dispositivos unidos a él, la combinación que comprende: una interfase de órdenes incluida en cada uno de tales subsistemas para transferir información entre dicho procesador central y dicho un subsistema inteligente, incluyendo dicha interfase de órdenes:una puerta de interfase de órdenes para recibir una orden directa o una orden indirecta proveniente de dicho procesador central, las cuales ordenes son indicativas del tipo de operación que ha de realizarse por el subsistema inteligente o los dispositivos unidos a él; yuna puerta de atención, para recibir desde dicho procesador central, un código que tenga una primera porción que es indicativa de cual de dichas órdenes directas o de dichas ordenes indirectas se recibe en dicha puerta de interfase de órdenes; y una segunda porción que es indicativa de cual de los sistemas inteligentes o de los dispositivos unidos a él ha de ejecutar la orden recibida en dicha puerta de interfase de órdenes".

公开(公告)号：CA2026768C

公开(公告)日：1996-07-23

申请号：CA2026768

申请日：1990-10-02

Applicant: IBM

Inventor： PADGETT RUSSELL S ,  CHISHOLM DOUGLAS R ,  GARCIA SERAFIN J E JR ,  ALVAREZ RAFAEL ,  KALMAN DEAN A ,  YODER ROBERT D

IPC: G06F12/06 ,  G06F12/02 ,  G06F13/16

Abstract: A selected address within one of two segments of a memory space of a second address/data bus, can be accessed from a first bus through one of two data registers. In addition, the location of the two segments within the memory space of the second bus is selectable through two segment registers, which are accessed from the first bus through the first data register. A two byte wide "mode" register, which can be directly accessed from the first bus, stores data within three ranges. When the mode register data is within the first range, a selected segment register can be accessed through the first data register. A first value within this range selects the first segment register, while a second value selects the second segment register. Data loaded into the first and second segment registers points to first and second segments of the second memory space, respectively. When the mode register data is within the second range, this data functions as a pointer to select an address within a selected segment. The selected address is accessed through the data registers; the first data register accessing the selected address in the first segment, while the second data register accesses the selected address in the second segment. After a selected address has been accessed, an auto-increment circuit increments the mode register so that the next sequential address in the selected segment can be accessed without having to reload the mode register. When the mode register data is within the first range, the two data registers can be directly accessed from the first bus.

公开(公告)号：CA1184308A

公开(公告)日：1985-03-19

申请号：CA425351

申请日：1983-04-06

Applicant: IBM

Inventor： BANNON ROBERT D ,  BHANSALI MAHENDRA M ,  CHISHOLM DOUGLAS R ,  FINNEY DAMON W ,  MINNICH WALTER D ,  SUAREZ GUSTAVO A

IPC: G06F11/10 ,  G06F12/16 ,  G06F11/00

Abstract: TRUE SINGLE ERROR CORRECTION SYSTEM A scheme for true error correction and multiple bit failure detection for a memory system using multiple data bits per chip. An H-Matrix results in syndrome generation of bits that are unique for single bit failures that will not match syndromes generated by multiple bit failures. All multiple bit failures are detected without miscorrecting any single bits that have not failed. Single pass logic employs all syndromes in parallel inputs to determine the presence of a single bit failure for subsequent correction and also detects the presence of multiple bit failures.

公开(公告)号：CA2026737C

公开(公告)日：1996-01-23

申请号：CA2026737

申请日：1990-10-02

Applicant: IBM

Inventor： GARCIA SERAFIN J E JR ,  CHISHOLM DOUGLAS R ,  KALMAN DEAN A ,  PADGETT RUSSELL S ,  YODER ROBERT D

IPC: G06F13/32 ,  G06F13/362 ,  G06F13/24

Abstract: A plurality of specialized controllers, each one adapted to control a particular type of data transfer operation, control the flow of data between a system bus and a local bus on a computer adapter card. When the Direct Memory Access (DMA) controller is controlling a DMA operation on the local bus, certain other controllers can break-in to the current DMA operation, temporarily halting the DMA operation until the other controller has completed its data transfer operation. To break-in to a DMA operation, handshaking signals between the DMA controller and the local bus interface circuit are temporarily blocked by blocking signals from a break-in logic circuit. The break-in circuit includes a four-state state machine to block the handshaking signals at the appropriate times, and to signal the interrupting controller to begin its data transfer operation. When breaking-in to a DMA operation in this manner, the operation of the DMA controller is not altered; instead, to the DMA controller, it appears that the local bus interface circuit is merely slow to respond with its acknowledge handshake.

公开(公告)号：CA1315890C

公开(公告)日：1993-04-06

申请号：CA598603

申请日：1989-05-03

Applicant: IBM

Inventor： CHISHOLM DOUGLAS R ,  ISEMINGER ROBERT G ,  KELLEY RICHARD A ,  LEUNG WAN L ,  MOYER JAMES T ,  SNEDAKER MARK C

IPC: G06F13/36 ,  G06F13/28

Abstract: In a computer system, a plurality of input/output processors (IOP's) are connected via an asynchronous input/output bus, called an "SPD" bus, to one side of an input/output interface controller (IOIC). The other side of the IOIC is connected to a storage controller (SC) via a synchronous bus called an "adapter" bus. The SC is connected to a common system memory and possibly also to an instruction processing unit. The SPD bus, which comprises three sub-buses and a control bus, conducts signals between each IOP and the IOIC in an asynchronous "handshaking" manner. The adapter bus, which comprises two sub-buses and a control bus, conducts signals between the IOIC and the SC in a synchronous manner. The IOIC, interconnected between the SPD bus and adapter bus, functions as a buffer between the faster synchronous bus and the slower asychronous bus. The IOIC also comprises at least one shared DMA facility for executing DMA storage operations requested by the IOP's via the SPD bus. Each shared DMA facility includes a buffer for control information and data to be transmitted between the SC and one of the IOP's and a bus interface coupled to the buffer, to the adapter bus and to the SPD bus for independently transferring the control information and data between the buffer and the SC, on one hand, via the adapter bus, and between the buffer and the one IOP, on the other hand, via the SPD bus. In this manner, the SPD bus can be released for utilization by other IOP's connected thereto during a period of "storage latency" after a DMA storage operation has been initiated by one IOP.

公开(公告)号：BR9005632A

公开(公告)日：1991-09-17

申请号：BR9005632

申请日：1990-11-07

Applicant: IBM

Inventor： GARCIA SERAFIN JOSE E JR ,  CHISHOLM DOUGLAS R ,  KALMAN DEAN A ,  PADGETT RUSSELL S ,  YODER ROBERT D

IPC: G06F13/32 ,  G06F13/362 ,  G06F13/28

Abstract: A plurality of specialized controllers, e.g. 202, 204 & 206, each one adapted to control a particular type of data transfer operation, control the flow of data between a system bus 104 and a local bus 106 on a computer adapter card 102. When the Direct Memory Access DMA controller 202 is controlling a DMA operation on the local bus, certain other controllers 204 & 206 can break-in to the current DMA operation, temporarily halting the DMA operation until the other controller has completed its data transfer operation. To break-in to a DMA operation, handshaking signals between the DMA controller and the local bus interface circuit 212 are temporarily blocked by blocking signals from a break-in logic circuit 210 . The break-in circuit includes a four-state state machine to block the handshaking signals at the appropriate times, and to signal the interrupting controller to begin its data transfer operation. When breaking-in to a DMA operation in this manner, the operation of the DMA controller is not altered; instead, to the DMA controller, it appears that the local bus interface circuit is merely slow to respond with its acknowledge handshake.

公开(公告)号：CA2026768A1

公开(公告)日：1991-05-14

申请号：CA2026768

申请日：1990-10-02

Applicant: IBM

Inventor： PADGETT RUSSELL S ,  CHISHOLM DOUGLAS R ,  GARCIA SERAFIN J E JR ,  ALVAREZ RAFAEL ,  KALMAN DEAN A ,  YODER ROBERT D

IPC: G06F12/06 ,  G06F12/02 ,  G06F13/16

Abstract: A selected address within one of two segments of a memory space (124) of a second address/data bus (116), can be accessed from a first bus (102) through one of two data registers (136 and 138). In addition, the location of the two segments within the memory space of the second bus is selectable through two segment registers (148 and 150), which are accessed from the first bus through the first data register (136). A two byte wide "mode" register (126 and 128), which can be directly accessed from the first bus, stores data within three ranges. When the mode register data is within the first range, a selected segment register can be accessed through the first data register. A first value within this range selects the first segment register (148), while a second value selects the second segment register (150). Data loaded into the first and second segment registers points to first and second segments of the second memory space, respectively. When the mode register data is within the second range, this data functions as a pointer to select an address within a selected segment. The selected address is accessed through the data registers; the first data register (136) accessing the selected address in the first segment, while the second data register (138) accesses the selected address in the second segment. After a selected address has been accessed, an auto-increment circuit increments the mode register so that the next sequential address in the selected segment can be accessed without having to reload the mode register. When the mode register data is within the third range, the two data registers can be directly accessed from the first bus.