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Patent Agency Ranking
公开(公告)号：BR7708548A
公开(公告)日：1978-08-15
申请号：BR7708548
申请日：1977-12-21
Applicant: IBM
Inventor： COMMANDER R , GARDNER P
Abstract: A data storage apparatus, such as an accessing head magnetic disk file, includes at least one data disk surface and a servo disk surface. In operation, a continuous position signal having high frequency components is derived from the servo surface, which has a quadature type servo signal prerecorded thereon. A circuit means modifies the derived position signal so that a substantially linear signal representing the displacement of the servo head from the servo track is obtained. A second position signal having a low frequency component is obtained from servo sector information registered on the data disk surface and together with the first position signal forms a hybrid position signal. This hybrid signal is used to control the movement of the data heads relative to the data tracks to ensure optimum transducing operation.
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公开(公告)号：SE353408B
公开(公告)日：1973-01-29
申请号：SE568870
申请日：1970-04-24
Applicant: IBM
Inventor： FLINDERS M , GARDNER P , HALLETT J , JONES J , MINSHULL J , TAYLOR K
Abstract: 1,265,013. Electric digital data storage: computers. INTERNATIONAL BUSINESS MACHINES CORP. 24 April, 1969, No. 20902/69. Headings G4A and G4C. Error detecting circuitry checks data transfer between two registers to provide an error signal only in the absence of a bit of one value in any order of the second register when the same order of the first register contains a bit of the one value. In Fig. 1 two associative stores 1, 2 storing the same information have a selector trigger 4 (to indicate match) for each word location 3, and each have two input/output registers 12, 13 for store 1 and 15, 16 for store 2. Register 13 can also feed and be fed by a bus 23, register 16 can be fed by bus 23, register 12 can be fed by a bus 24, and register 15 can feed and be fed by bus 24, via drivers 26, 30 and receivers 25, 26, 28, 29. One or more further pairs of associative stores may be connected to the buses 23, 24 as may non-associative stores, and the buses communicate with each other via a buffer which may be in the main memory of a computer system using the invention or may be a single separate register. Error features.-During simultaneous associative search in stores 1 and 2 using the same search argument from registers 12, 15 or 13, 16, comparators 6 produce an error signal if different selector triggers 4 are set by the two stores. After read, comparators 18 produce an error signal if input/output registers 12 and 15, or 13 and 16, have unequal contents (only one pair of registers is loaded from the store). Following this, to transfer out the read information and prepare for the next associative search, registers 13, 15 are gated (by actuating drivers 26, 30) to buses 23, 24 respectively, the buses being gated (by actuating receivers 27, 28) to registers 16, 12 almost immediately afterwards. An error signal is now produced unless there is a 1 in register 12 for each 1 in register 15 and a 1 in register 16 for each 1 in register 13 (this form of check being used since other stores may be using the buses simultaneously so a simple equal/unequal check cannot be used). Parity circuits 31, 33 connected in series, generate the parity of the data being supplied to registers 12, 16 from the buses 24, 23 (see above) and this parity is compared (not shown) with parity generated for the data on the buses by two parity circuits (not shown) connected to the respective buses and in series with each other, an error signal being produced on inequality. The buses 23, 24 are now gated (by actuating receivers 25, 29) to the registers 13, 15. An error signal is produced if registers 12 and 15, or 13 and 16, are now unequal as determined by comparators 18. After a write operation, all the receivers are actuated to load registers 12, 13, 15, 16 from the buses for the next associative search, parity checking, and an inequality check by 18, being done as above. After associative interrogation, an extra check on the drivers 26, 30 is done by inhibiting all drivers (of all pairs of stores linked to the buses) and generating the parity of the data on the buses, an error signal being produced if it is non-zero. Detection of any error causes retry (repetitive) of the storage cycle giving the error. If this is unsuccessful and the error can be attributed to data errors, an incorrect word is replaced by its duplicate from the other store 1 or 2 followed by retry. If still unsuccessful, or if the error cannot be attributed to data errors, lines 42, 43 are de-energized to isolate the pair of stores from the buses. If the error signal came from mismatched selector triggers 4, the selector triggers are reset (their states having been saved in a diagnostic column of each store 1, 2), then set in turn by a " next " operation which causes a 1 to shift down each column of triggers 4. If the is do not arrive at the bottoms of the columns simultaneously (even after retires) the the stores are isolated from the buses. If they do arrive simultaneously a read operation is performed and if comparators 18 (which should be comparing zeroes) detect inequality, the selector triggers 4 are not resetting properly, so the stores are isolated from the buses. If this does not happen, the " next " operation is good, and is used repeatedly to read out successive bits of the diagnostic columns for comparison at 18, inequality causing the rest of the words corresponding to the unequal diagnostic column bits to be read out for parity checks (by means not shown). If both words have correct parity, the stores are isolated, but if only one is correct, the incorrect word is replaced by the correct one via the two buses. Fig. 6 (not shown) shows two stages of a parity circuit having a stage for each bit position of a word whose parity is to be generated. A typical stage comprises a transistor tree controlled by a parity input in true and complement form from the preceding stage, and by the corresponding bit of the word, to produce a parity output in true and complement form to the next stage. The circuit can also be used for checking parity. Fig. 7 (not shown) shows one stage of a comparator, having outputs indicating (A and not B), (B and not A) respectively, where A, B are the bits being compared. Both outputs are sensed for the inequality comparison and only one for the ones comparison above.
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公开(公告)号：SE337131B
公开(公告)日：1971-07-26
申请号：SE940869
申请日：1969-07-02
Applicant: IBM
Inventor： TITMAN P , LLEWELYN R , GARDNER P , HALLETT M
Abstract: 1,218,406. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 4 July, 1968, No. 32075/68. Heading G4A. An electronic data processing system includes two associative stores, data from one being used for an associative search in the other. General.-The system of Fig. 2 has three associative stores 21, 22, 23 each stored word having the fields shown. The local store 23 contains macro-instructions and operands, the working store 22 contains tables and the control store 21 contains sequences of micro-instructions for executing respective macro-instructions. In each store, matching may be done on the complete words or on portions indicated by the " mask " lines, and data read from or written into whole words or the portions not indicated by the respective mask lines. A match can set selectively a primary or a secondary trigger associated with the matched word, or a primary or secondary trigger associated with the next word. Reading and writing occurs with respect to that word or words having selectively either the primary trigger set or ther secondary trigger set, and if there is more than one such word the same data will be written into all such words (on writing) or the data read from the various words (on reading) will be ORed together. The set state of a primary or secondary trigger may be moved to the next such trigger for the same store, by a " next " operation. Each storage cell has three possible states 0, 1, X, the last being a " don't care " state which will match on either 0 or 1 indifferently. The macro-instructions are stored in consecutive locations in the local store, the first having a predetermined L.S. TAG field, successive macro-instructions being obtained by use of the " next " operation to step the set state of a primary trigger to the next primary trigger. The DATA 1 field of the macroinstruction is matched against the C.S. TAG fields of the control store to obtain the first micro-instruction, further micro-instructions being obtained by use of the " next " operation on the primary triggers of the store, similar to above. The L.S. TAG field of a micro-instruction can be matched against the L.S. TAG fields of the local store to obtain operands which are matched against the DATA 0 fields of the working store as the W.S. TAG of the microinstruction is matched against the W.S. TAG fields of the working store. The W.S. TAG applied specifies a stored table and the operands specify a word (or the first of a plurality of consecutive words) therein which contain the result of an operation on the operands (table look-up). The result can be transferred to the local store. The W.S. and L.S. TAGS matched against the working and local stores also control operation of the respective stores, and the control store is controlled by the C.S. OP field from itself. Micro-instruction subroutines can be sequenced through using the secondary triggers of the control store without disturbing the primary triggers used for sequencing through the main microprogramme in which the subroutine is embedded. Specifications 1,127,270 and 1,186,703 are referred to for the associative stores. Further details of table look-up.-Fig. 3 shows part of the working store for performing the AND, OR and EXCL-OR of two 4-bit operands A, B. The operands and a tag (which is 01, 11, 10 for AND, OR, EXCL-OR respectively) are matched against the corresponding " argument " fields shown in each word (row) the " output " fields of matching rows (there will be only one for AND, two for EXCL-OR and three for OR) being read out and ORed together. Shift and addition by table look-up are mentioned. Branch.-Micro-instruction branch is performed by obtaining the next micro-instruction by matching a 4-bit COND field from the working store and the C.S. TAG from the current micro-instruction (modified by ORing with the DATA 1 field from the working store, which will, however, usually be all zeros, or by the DATA 1 field from the local store) against the COND and C.S. TAG fields of the control store. The COND field from the working store indicates machine conditions, e.g. which of two operands is the larger, or overflow during addition. Macro-instruction branch is done similarly (in the local store) except that no COND field is involved. Modifications.-A conventional core store can be provided for holding the macro-instructions, its data input/output and address register both communicating with buses 27, 28 of Fig. 2. The core store is controlled by the W.S. TAGs from the control store (bus 24). An error (e.g. in an address) causes the core store to emit a C.S. TAG on bus 28 to cause entry into a diagnostic routine (no details). The local store holds instruction counts (for obtaining the next macro-instruction from the core store) which can be indexed by +1, +2, or -1 obtained from the working store, the indexing being by table look-up in the working store. The control store may be partly non-associative. Combination with second system.-The above system may be used as an interface between a transmission line and a larger data processing system, data from the line being buffered in the working store, then checked and edited before transfer to the larger system.
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