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    DATA PROCESSING SYSTEM
    2.
    发明专利
    DATA PROCESSING SYSTEM 未知

    公开(公告)号：CA935940A

    公开(公告)日：1973-10-23

    申请号：CA66919

    申请日：1969-11-07

    Applicant: IBM

    Inventor： MINSHULL J ,  LLEWELYN R

    IPC: G06F9/26 ,  G06F9/22 ,  G06F9/32 ,  G06F9/34 ,  G06F9/38 ,  G06F12/08 ,  G11C15/04

    Abstract: 1,234,484. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 12 Nov., 1968, No. 53517/68. Heading G4A. An electronic data processing system comprises a control store controlling (a) execution of functions by table-look-up procedures in an associative working store and (b) execution by table-look-up procedures in an associative address store of functions on address data to be used in addressing a non-associative data store in the system, the arrangement being such that simultaneous execution can take place in the working and address stores. The control store, which is associative, supplies tags for interrogating the associative working and address stores and an associative local store (which comprises registers). A 4-byte ADD instruction is read, two bytes at a time, from the data store addressed from an instruction counter in the address store, the op code being interpreted in the working store to select the microprogramme used to access the operands. The instruction specifies the register holding the first operand, and a displacement and two further registers, the displacement and contents of the two further registers being added serially by byte using table-look-up in the working store to obtain the address in the data store of the second operand. This address, supplied serially by byte as formed, is inserted into the right-most byte position of the input-output register of the address store and shifted along utilizing tablelook-up in a shift table in the address store, until the whole address is present when it is used for addressing the data store. Shift.-Each word in the shift table has a single 1, every other bit being a " don't care," and successive words have the 1 in positions 1, 1; 2, 1; 3, 1; 4, 1; 1, 2; 2,2; 3, 2; 4,2; 1, 3 &c., where the first digit is the byte position and the second is the bit position, numbered from the right. As each byte arrives in the input-output register, the register is used to interrogate all the words in the shift table and the word immediately following each word giving a match is read out, these words being read out simultaneously, corresponding bits being ORed, the result going into the input-output register. Invalid address check.-The associative address store may have a table for detecting any 1 bit in the highest order byte or lowest order bit of an address, each word in the table having a single 1 bit in a different position for interrogating, the other bits interrogated being " don't cares," a match causing read out of an error 1 bit. Alternatively, such error 1 bits may be included in the shift table for the same purpose. Specifications Nos. 1,127,270, 1,186,703, 1,218,406 are referred to, the first two for suitable associative stores and the last as being a system of which the present invention is a modification.

    4.
    发明专利
    未知

    公开(公告)号：SE337131B

    公开(公告)日：1971-07-26

    申请号：SE940869

    申请日：1969-07-02

    Applicant: IBM

    Inventor： TITMAN P ,  LLEWELYN R ,  GARDNER P ,  HALLETT M

    IPC: G06F9/26 ,  G06F9/28 ,  G11C15/04 ,  G06F9/00

    Abstract: 1,218,406. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 4 July, 1968, No. 32075/68. Heading G4A. An electronic data processing system includes two associative stores, data from one being used for an associative search in the other. General.-The system of Fig. 2 has three associative stores 21, 22, 23 each stored word having the fields shown. The local store 23 contains macro-instructions and operands, the working store 22 contains tables and the control store 21 contains sequences of micro-instructions for executing respective macro-instructions. In each store, matching may be done on the complete words or on portions indicated by the " mask " lines, and data read from or written into whole words or the portions not indicated by the respective mask lines. A match can set selectively a primary or a secondary trigger associated with the matched word, or a primary or secondary trigger associated with the next word. Reading and writing occurs with respect to that word or words having selectively either the primary trigger set or ther secondary trigger set, and if there is more than one such word the same data will be written into all such words (on writing) or the data read from the various words (on reading) will be ORed together. The set state of a primary or secondary trigger may be moved to the next such trigger for the same store, by a " next " operation. Each storage cell has three possible states 0, 1, X, the last being a " don't care " state which will match on either 0 or 1 indifferently. The macro-instructions are stored in consecutive locations in the local store, the first having a predetermined L.S. TAG field, successive macro-instructions being obtained by use of the " next " operation to step the set state of a primary trigger to the next primary trigger. The DATA 1 field of the macroinstruction is matched against the C.S. TAG fields of the control store to obtain the first micro-instruction, further micro-instructions being obtained by use of the " next " operation on the primary triggers of the store, similar to above. The L.S. TAG field of a micro-instruction can be matched against the L.S. TAG fields of the local store to obtain operands which are matched against the DATA 0 fields of the working store as the W.S. TAG of the microinstruction is matched against the W.S. TAG fields of the working store. The W.S. TAG applied specifies a stored table and the operands specify a word (or the first of a plurality of consecutive words) therein which contain the result of an operation on the operands (table look-up). The result can be transferred to the local store. The W.S. and L.S. TAGS matched against the working and local stores also control operation of the respective stores, and the control store is controlled by the C.S. OP field from itself. Micro-instruction subroutines can be sequenced through using the secondary triggers of the control store without disturbing the primary triggers used for sequencing through the main microprogramme in which the subroutine is embedded. Specifications 1,127,270 and 1,186,703 are referred to for the associative stores. Further details of table look-up.-Fig. 3 shows part of the working store for performing the AND, OR and EXCL-OR of two 4-bit operands A, B. The operands and a tag (which is 01, 11, 10 for AND, OR, EXCL-OR respectively) are matched against the corresponding " argument " fields shown in each word (row) the " output " fields of matching rows (there will be only one for AND, two for EXCL-OR and three for OR) being read out and ORed together. Shift and addition by table look-up are mentioned. Branch.-Micro-instruction branch is performed by obtaining the next micro-instruction by matching a 4-bit COND field from the working store and the C.S. TAG from the current micro-instruction (modified by ORing with the DATA 1 field from the working store, which will, however, usually be all zeros, or by the DATA 1 field from the local store) against the COND and C.S. TAG fields of the control store. The COND field from the working store indicates machine conditions, e.g. which of two operands is the larger, or overflow during addition. Macro-instruction branch is done similarly (in the local store) except that no COND field is involved. Modifications.-A conventional core store can be provided for holding the macro-instructions, its data input/output and address register both communicating with buses 27, 28 of Fig. 2. The core store is controlled by the W.S. TAGs from the control store (bus 24). An error (e.g. in an address) causes the core store to emit a C.S. TAG on bus 28 to cause entry into a diagnostic routine (no details). The local store holds instruction counts (for obtaining the next macro-instruction from the core store) which can be indexed by +1, +2, or -1 obtained from the working store, the indexing being by table look-up in the working store. The control store may be partly non-associative. Combination with second system.-The above system may be used as an interface between a transmission line and a larger data processing system, data from the line being buffered in the working store, then checked and edited before transfer to the larger system.

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