公开(公告)号：JPH04278285A

公开(公告)日：1992-10-02

申请号：JP32818191

申请日：1991-11-15

Applicant: IBM

Inventor： GARII BERA BURONAA ,  SAN HOO DON ,  UEI WANGU

IPC: G11C11/407 ,  G11C11/408 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PURPOSE: To shorten access time by driving a word line with a circuit maintaining the gate of an access transistor to negative potential through the use of DRAM using a word driving circuit reducing the word line to negative potential. CONSTITUTION: The voltage of the word line 10 is raised by using a constant negative voltage generation circuit 26 and a trench capacitor 25. Negative potential generated on a chip by the circuit 26 is stored in a capacitor 25 having capacitance which is considerably larger than that of the line 10. The word line driving circuit is constituted of an NMOS reducing transistor Tr24 and a PMOS raising Tr23. When negative potential is supplied to the source of 24, negative potential is supplied to the line 10 when Tr24 is gated to a conductive state since Tr is switched. Then, Tr23 is connected to the drain of Tr24 in series and the line 10 can be driven in a positive direction.