公开(公告)号：JPH10188570A

公开(公告)日：1998-07-21

申请号：JP33003897

申请日：1997-12-01

Applicant: IBM

Inventor： LATTIMORE GEORGE M ,  TERRY L REJA ,  GASS W YUNG

IPC: G11C11/412

Abstract: PROBLEM TO BE SOLVED: To provide a five-transistor memory cell, which is a single-ended static random access memory(SRAM) cell. SOLUTION: Read/write operation from a cell is realized by using a word line read signal 111, a word line write signal 113, and a bit line 110. One of the transistors 104 in a memory cell is connected to a impedance-controlled node vgnd 112, rather than directly connected to a ground. Thereby affected transistors can float between the ground and high impedance condition, which enables writing to a memory cell through one bit line.