公开(公告)号：JPH10188565A

公开(公告)日：1998-07-21

申请号：JP33033797

申请日：1997-12-01

Applicant: IBM

Inventor： MICHAEL K SHIRAURA ,  LATTIMORE GEORGE M ,  GASS WAI-YANG YUNG

IPC: G11C11/41 ,  G11C7/12 ,  G11C7/22 ,  G11C11/417 ,  G11C11/419

Abstract: PROBLEM TO BE SOLVED: To provide an SRAM structure capable of reducing the power consumption by conditionally restoring only a memory cell to be evaluated. SOLUTION: A device has arbitrary number of memory cells 72, multiple word lines 76, and multiple predecoded address lines 78 and 80, which enable to select one line from the multiple word lines 76. The memory cells 72 are arrayed in a group 74, and each group has a connected bit line. A precharge circuit is connected to the bit line to restore a specified cell of the memory cells 72, after the evaluating operation. The predecoded address lines 78 and 80 provide encoded information concerning the address related to the evaluated memory cells 72, and a decoder identifies the address to determine which word line to use for accessing the evaluated memory cells 72.

公开(公告)号：JPH10187552A

公开(公告)日：1998-07-21

申请号：JP27749997

申请日：1997-10-09

Applicant: IBM

Inventor： LATTIMORE GEORGE M ,  ROBERT P MASLEYD ,  JOHN S MUHICHI

IPC: G06F12/16 ,  G11C8/12 ,  G11C29/00 ,  G11C29/04

Abstract: PROBLEM TO BE SOLVED: To overcome a defect in a circuit of a semiconductor element by including memory cells and a word line decoder connected to only the memory cells in a redundant memory array. SOLUTION: A subarray 324 includes the word line decoder 202, the memory cells 204, a bit line decoder 206, and an input/output circuit 208. The word line decoder 202 is connected to the memory cells 204 and provides pieces of decoded data. Further, the bit line decoder 206 is connected to the memory cells 204 and communicates decoded data or data to be decoded. The input/ output circuit 208 is connected to the bit line decoder 206, which communicates data to the bit line decoder 206 to determine a value corresponding to the data. The subarray 324 has substantially the same structure with other subarrays which are shown here.

公开(公告)号：JPH10188570A

公开(公告)日：1998-07-21

申请号：JP33003897

申请日：1997-12-01

Applicant: IBM

Inventor： LATTIMORE GEORGE M ,  TERRY L REJA ,  GASS W YUNG

IPC: G11C11/412

Abstract: PROBLEM TO BE SOLVED: To provide a five-transistor memory cell, which is a single-ended static random access memory(SRAM) cell. SOLUTION: Read/write operation from a cell is realized by using a word line read signal 111, a word line write signal 113, and a bit line 110. One of the transistors 104 in a memory cell is connected to a impedance-controlled node vgnd 112, rather than directly connected to a ground. Thereby affected transistors can float between the ground and high impedance condition, which enables writing to a memory cell through one bit line.

公开(公告)号：JPH10187798A

公开(公告)日：1998-07-21

申请号：JP29374397

申请日：1997-10-27

Applicant: IBM

Inventor： LATTIMORE GEORGE M ,  ROBERT P MASREED ,  JOHN S MYUUHIHI

IPC: H01L21/822 ,  G06F12/08 ,  G06F15/78 ,  G06F17/50 ,  G11C5/02 ,  H01L21/82 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a method and device for a cache subarray used in microprocessor integrated circuit. SOLUTION: A processor unit is arranged in the center area of a microprocessor integrated circuit, the peripheral area is specified as a cache memory array area, and a specified number of cache memory subarrays are arranged in the peripheral area while surrounding the center area so that a variable-size cache memory array is efficiently arranged. The cache memory subarray includes a part, where one cache word is fixed. The microprocessor integrated circuit itself has a modular cache memory array of variable size, the peripheral area which is specified as the cache memory array area and surrounds the center area, and the specific cache memory subarrays arranged in the peripheral area so as to constitute the cache memory array.

公开(公告)号：DE10105627B4

公开(公告)日：2007-06-21

申请号：DE10105627

申请日：2001-02-08

Applicant: IBM

Inventor： LATTIMORE GEORGE M ,  PILLE JUERGEN ,  SAUTER ROLF ,  WENDEL DIETER

IPC: G11C7/00 ,  G06F9/30 ,  G11C7/10 ,  G11C7/22 ,  G11C11/417

公开(公告)号：DE10105627A1

公开(公告)日：2001-10-04

申请号：DE10105627

申请日：2001-02-08

Applicant: IBM

Inventor： LATTIMORE GEORGE M ,  PILLE JUERGEN ,  SAUTER ROLF ,  WENDEL DIETER

IPC: G06F9/30 ,  G11C7/10 ,  G11C7/22 ,  G11C7/00

Abstract: The operating method for a multi-pin storage device is adapted for a device having two or more memory arrangements (201,202) in order to reduce the amount of cabling surface required and includes a multiplexer for each two or more associated read terminals of the memory arrangements. First data is written to a first memory array of the first memory arrangement (201) and second data is written to a first memory array of a second memory arrangement (202), and the first memory array of the second memory arrangement is also designated by the same first address.

公开(公告)号：MY120522A

公开(公告)日：2005-11-30

申请号：MYPI9705018

申请日：1997-10-24

Applicant: IBM

Inventor： LATTIMORE GEORGE M ,  LEASURE TERRY L ,  YEUNG GUS W

IPC: G06F12/00 ,  G06F12/08 ,  G11C29/00

Abstract: A SET ASSOCIATIVE CACHE MEMORY ARRAY INCLUDES REDUNDANT MEMORY PORTIONS (311, 406) FOR USE IN THE CASE OF A DEFECTIVE PORTION OF THE MEMORY. INFORMATION IS STORED WITHIN THE DEFECTIVE PORTION OF THE MEMORY ARRAY AND AN IDENTICAL COPY IS STORED WITHIN THE REDUNDANT PORTION. ADDITIONALLY, READING OF THE INFORMATION IS DONE FROM BOTH THE DEFECTIVE PORTION AND THE REDUNDANT PORTION. SELECTION OF THE INFORMATION FROM EITHER THE DEFECTIVE PORTION OR THE REDUNDANT PORTION IS MADE USING PROGRAMMABLE CIRCUITRY SUCH AS A FUSE (308, 330).

公开(公告)号：SG55403A1

公开(公告)日：1998-12-21

申请号：SG1997003876

申请日：1997-10-27

Applicant: IBM

Inventor： LATTIMORE GEORGE M ,  LEASURE TERRY L ,  YEUNG GUS W

IPC: G06F12/08 ,  G11C29/00 ,  G06F12/16

Abstract: A set associative cache memory array includes redundant memory portions for use in the case of a defective portion of the memory. Information is stored within the defective portion of the memory array and an identical copy is stored within the redundant portion. Additionally, reading of the information is done from both the defective portion and the redundant portion. Selection of the information from either the defective portion or the redundant portion is made using programmable circuitry such as a fuse.