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Patent Agency Ranking
公开(公告)号：DE3850192D1
公开(公告)日：1994-07-21
申请号：DE3850192
申请日：1988-08-23
Applicant: IBM
Inventor： ANDERSON ROBERT WHITCOMB , GEE RALPH LEONARD , INDELICATO JASPER ANTHONY , PATEL ARVIND MOTIBHAI
Abstract: The invention relates to a method of correcting errors in encoded uncorrected data in a disk storage device, employing a multiple level error correction code for use with records of varying length, including initially formatting the data into blocks, each comprising subblocks, which, except for possibly the last, are of equal size, the number of subblocks in any record being determined by the length of that record. The method is characterised by the steps of statistically determining, as a function of subblock size, first level correction capability and the length of the longest record anticipated, a number representing the minimum number of subblocks which may be in error and correctable; transmitting the uncorrected data to a storage director; performing at least a portion of the first level of error correction at the storage device; and, after all uncorrected data has been received by the storage director, transmitting error information reflecting first level error pattern and location to the storage director for completion of the first level of correction and performance of subsequent levels of correction. The invention also relates to apparatus for performing a method of correcting errors as above.
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公开(公告)号：DE3850192T2
公开(公告)日：1995-01-12
申请号：DE3850192
申请日：1988-08-23
Applicant: IBM
Inventor： ANDERSON ROBERT WHITCOMB , GEE RALPH LEONARD , INDELICATO JASPER ANTHONY , PATEL ARVIND MOTIBHAI
Abstract: The invention relates to a method of correcting errors in encoded uncorrected data in a disk storage device, employing a multiple level error correction code for use with records of varying length, including initially formatting the data into blocks, each comprising subblocks, which, except for possibly the last, are of equal size, the number of subblocks in any record being determined by the length of that record. The method is characterised by the steps of statistically determining, as a function of subblock size, first level correction capability and the length of the longest record anticipated, a number representing the minimum number of subblocks which may be in error and correctable; transmitting the uncorrected data to a storage director; performing at least a portion of the first level of error correction at the storage device; and, after all uncorrected data has been received by the storage director, transmitting error information reflecting first level error pattern and location to the storage director for completion of the first level of correction and performance of subsequent levels of correction. The invention also relates to apparatus for performing a method of correcting errors as above.
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公开(公告)号：DE69022122D1
公开(公告)日：1995-10-12
申请号：DE69022122
申请日：1990-06-06
Applicant: IBM
Inventor： CHUNG PAUL WINGSHING , GEE RALPH LEONARD , LANG LUKE CHUNG KUANG , SABER PAIK
Abstract: A means for setting the free-running frequency of a voltage controlled oscillator (VCO) (12) without requiring laser trimming or the like is described. The VCO forms part of an interconnected phase-locked loop (PLL) and frequency-locked loop (FLL). At system power on, the PLL is automatically disabled and a digital-to-analog (DAC) (11) in the PLL is set to a value corresponding substantially to the centre of a preselected lock range. The FLL, which includes a second DAC (10), then operates to generate a bias voltage for incrementing or decrementing the VCO output frequency until the VCO pulse count stored in a register equals an expected count; whereupon the VCO will be set at its free-running frequency. When the PLL is enabled, a phase error generator (14) generates a digital phase error signal from the input data. A digital integrator (19) converts the phase error signal to a digital frequency error signal. These error signals are added and the result is supplied to the DAC in the PLL for providing an analog output indicative of PLL frequency error. The outputs from both DACs are summed and the resultant current is converted to a bias voltage to adjust the VCO frequency as necessary for normally maintaining it within said lock range. If the VCO frequency deviates from said range, the frequency error signal to the PLL DAC is zeroed, and the frequency error signal is supplied to the FLL DAC. The phase error signal from the PLL DAC and the signal from the FLL DAC as modified by the frequency error signal are summed, and the resultant current in converted to a bias voltage to adjust the VCO frequency to within said lock range.
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公开(公告)号：SG44439A1
公开(公告)日：1997-12-19
申请号：SG1996000397
申请日：1991-03-14
Applicant: IBM
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公开(公告)号：DE69022122T2
公开(公告)日：1996-05-02
申请号：DE69022122
申请日：1990-06-06
Applicant: IBM
Inventor： CHUNG PAUL WINGSHING , GEE RALPH LEONARD , LANG LUKE CHUNG KUANG , SABER PAIK
Abstract: A means for setting the free-running frequency of a voltage controlled oscillator (VCO) (12) without requiring laser trimming or the like is described. The VCO forms part of an interconnected phase-locked loop (PLL) and frequency-locked loop (FLL). At system power on, the PLL is automatically disabled and a digital-to-analog (DAC) (11) in the PLL is set to a value corresponding substantially to the centre of a preselected lock range. The FLL, which includes a second DAC (10), then operates to generate a bias voltage for incrementing or decrementing the VCO output frequency until the VCO pulse count stored in a register equals an expected count; whereupon the VCO will be set at its free-running frequency. When the PLL is enabled, a phase error generator (14) generates a digital phase error signal from the input data. A digital integrator (19) converts the phase error signal to a digital frequency error signal. These error signals are added and the result is supplied to the DAC in the PLL for providing an analog output indicative of PLL frequency error. The outputs from both DACs are summed and the resultant current is converted to a bias voltage to adjust the VCO frequency as necessary for normally maintaining it within said lock range. If the VCO frequency deviates from said range, the frequency error signal to the PLL DAC is zeroed, and the frequency error signal is supplied to the FLL DAC. The phase error signal from the PLL DAC and the signal from the FLL DAC as modified by the frequency error signal are summed, and the resultant current in converted to a bias voltage to adjust the VCO frequency to within said lock range.
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