公开(公告)号：JPH0620469A

公开(公告)日：1994-01-28

申请号：JP8167393

申请日：1993-04-08

Applicant: IBM

Inventor： GEIRII BERA BURONNAA ,  SANGU FUU DONGU

IPC: G11C11/407 ,  G11C5/14 ,  G11C11/409

Abstract: PURPOSE: To reduce a well noise by floating the potential of array well during the development of a bit line signal. CONSTITUTION: A transistor 98 is gate-controlled through a high/low signal from a control signal generator 100 that takes in timing and a control signal 102. Therefore, the potential of an array well 90 can be easily floated by pulling down a gate signal to the transistor 98, immediately before floating a bit line, during the bit signal development period of a read cycle. With an access device turned on, a differential bit line signal develops. Once a sense amplifier is latched, the array well is reconnected to a well potential generator 94 for the purpose of controlling a noise influence.