公开(公告)号：JPH04232688A

公开(公告)日：1992-08-20

申请号：JP21940791

申请日：1991-08-06

Applicant: IBM

Inventor： SANGU FUU DONGU ,  ROBAATO ROISU FURANCHI ,  UEI UANGU

IPC: G11C11/401 ,  G11C11/406 ,  G11C29/00 ,  G11C29/04

Abstract: PURPOSE: To prolong refresh interval by replacing a DRAM cell of a short data hold time with a redundant static memory cell. CONSTITUTION: Charges stored in capacity in the DRAM cell are discharged to an allowable level or below after a prescribed time interval T1 in many cells, and are discharged to the allowable level or below after a shorter time interval T2 in few cells. The refresh cycle of the DRAM is adjusted so as to become longer than the T2. This DRAM circuit contains plural redundant storage cells 50, a decoder receiving the addresses of the cells and a switch circuit. The decoder generates a first output when the receiving address is the address of the many cells, and generates a second output when the receiving address is the address of the few cells. The switch circuit allows to access the redundant storage cell in response to the first output to block the access of the few cells.

公开(公告)号：JPH0620469A

公开(公告)日：1994-01-28

申请号：JP8167393

申请日：1993-04-08

Applicant: IBM

Inventor： GEIRII BERA BURONNAA ,  SANGU FUU DONGU

IPC: G11C11/407 ,  G11C5/14 ,  G11C11/409

Abstract: PURPOSE: To reduce a well noise by floating the potential of array well during the development of a bit line signal. CONSTITUTION: A transistor 98 is gate-controlled through a high/low signal from a control signal generator 100 that takes in timing and a control signal 102. Therefore, the potential of an array well 90 can be easily floated by pulling down a gate signal to the transistor 98, immediately before floating a bit line, during the bit signal development period of a read cycle. With an access device turned on, a differential bit line signal develops. Once a sense amplifier is latched, the array well is reconnected to a well potential generator 94 for the purpose of controlling a noise influence.

公开(公告)号：JPH04291091A

公开(公告)日：1992-10-15

申请号：JP29253491

申请日：1991-10-11

Applicant: IBM

Inventor： SANGU FUU DONGU ,  UEI WANGU ,  HIYUN JIYONGU SHIN

IPC: G11C11/409 ,  G11C11/407 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/094

Abstract: PURPOSE: To prevent the chip area of DRAM from being considerably reduced through the use of an output driving circuit which does not need two PMOS pull-up transistors which are stacked for interfacing low on chip power voltage against off chip bus voltage. CONSTITUTION: An on-chip pump circuit generates voltage required at the time of interfacing an external bus in a first execution example. In a second execution example, external bus voltage is detected and external bus voltage is compared with on-chip VDD at the time of a try state. A third execution example is the combination of the first and second execution examples. The external bus is compared with VDD in the second execution example. Voltage higher than VDD is generated in the on-chip as in the first execution example. Voltage generated in the pertinent on-chip is used for controlling the PMOS pull-up device when bus voltage is higher than VDD instead of bus voltage.