公开(公告)号：GB2456363A

公开(公告)日：2009-07-15

申请号：GB0820474

申请日：2008-11-10

Applicant: IBM

Inventor： BAROWSKI HARRY ,  NIGGEMEIER TIM ,  GEMMEKE TOBIAS

IPC: G06F1/32 ,  G06F17/50

Abstract: The invention relates to a method and a system for analyzing and optimizing clock gating within a functional unit of an electronic design with a plurality of latches (10). In this method, a simulation of the design is performed to obtain clock activation signals (50) and data latch output signals (60) of said latches (10); by analyzing these data (50, 60) for the latches (10) at various clock cycles (ti), clock cycles (ti) are extracted when a given latch (10) may be clock gated. Specifically, the method comprises the steps of generating a latch clock activation matrix (100) containing clock activation and data switching information for each latch (10), identifying potentially unnecessary clock activity and deriving an improved clock gating design by eliminating unnecessary clock activity. Simulations can be performed on a HDL model. A verification check may be employed.