公开(公告)号：GB2498310B

公开(公告)日：2014-03-12

申请号：GB201307552

申请日：2011-10-21

Applicant: IBM

Inventor： BAROWSKI HARRY ,  HUBER ANDREAS ,  HARRER HUBERT ,  NIGGEMEIER TIM ,  SUPPER JOCHEN ,  MICHEL BRUNO ,  BRUNSCHWILER THOMAS ,  PAREDES STEPHAN

IPC: H01L23/50 ,  H01L23/36

Abstract: A mechanism is provided for integrated power delivery and distribution via a heat sink. The mechanism comprises a processor layer coupled to a signaling and input/output (I/O) layer via a first set of coupling devices and a heat sink coupled to the processor layer via a second set of coupling devices. In the mechanism, the heat sink comprises a plurality of grooves on one face, where each groove provides either a path for power or a path for ground to be delivered to the processor layer. In the mechanism, the heat sink is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism and the signaling and I/O layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

公开(公告)号：DE112020000193T5

公开(公告)日：2021-09-02

申请号：DE112020000193

申请日：2020-01-16

Applicant: IBM

Inventor： FRISCH ALBERT ,  BAROWSKI HARRY ,  STEENKEN DOMINIK ,  BUCHER DAVID ,  KUS GAWEL ,  HAIDE ISABEL ,  MUEGGENBURG JAN

IPC: G06N10/00

Abstract: Eine Quantenschaltungsanordnung (100) mit zumindest einer Quantenschaltung (110) zum Ausführen einer Berechnung auf einem Quantencomputer, wobei die Quantenschaltungsanordnung (100) zumindest eine Suchstruktur (50), die zum Ermitteln eines Wertes einer vordefinierten Funktion auf Grundlage einer durch einen Satz von Qubits (12, 14, 16, 18) dargestellten Variablen ausgebildet ist, und eine Klasseneinteilungsstruktur (60) aufweist, die zum Erkennen einer vorgegebenen Klasse (64, 66) auf Grundlage der Variablen ausgebildet ist, wobei die Suchstruktur (50) dazu gestaltet ist, den Wert der vordefinierten Funktion auf Grundlage der Klasse (64, 66) zu ermitteln. Des Weiteren ein auf einem klassischen Computer implementierbares Verfahren zum Kompilieren einer Quantenschaltungsanordnung (100) mit zumindest einer Quantenschaltung (110) zum Ausführen einer Berechnung auf einem Quantencomputer.

公开(公告)号：DE112011102966T5

公开(公告)日：2013-06-27

申请号：DE112011102966

申请日：2011-10-21

Applicant: IBM

Inventor： BAROWSKI HARRY ,  HARRER HUBERT ,  SUPPER JOCHEN ,  MICHEL BRUNO ,  HUBER ANDREAS ,  NIGGEMEIER TIM ,  BRUNSCHWILER THOMAS ,  PAREDES STEPHAN

IPC: H01L25/18

Abstract: Es wird ein Mechanismus zur integrierten Stromversorgung und Stromverteilung über einen Kühlkörper bereitgestellt. Der Mechanismus weist eine Prozessorschicht auf, die über eine erste Menge von Verbindungseinheiten mit einer Signalisierungs- und Eingabe/Ausgabe-Schicht (E/A-Schicht) verbunden ist, sowie einen Kühlkörper, der über eine zweite Menge von Verbindungseinheiten mit der Prozessorschicht verbunden ist. Bei dem Mechanismus weist der Kühlkörper eine Vielzahl von Nuten auf, wobei jede Nut entweder einen Pfad für Strom oder einen Pfad für Masse bereitstellt, die der Prozessorschicht zugeführt werden sollen. Bei dem Mechanismus ist der Kühlkörper nur zur Zufuhr von Strom vorgesehen und stellt den Elementen des Mechanismus keine Datenaustauschsignale bereit, und die Signalisierungs- und E/A-Schicht ist nur zum Übertragen der Datenaustauschsignale an die Prozessorschicht und zum Empfangen der Datenaustauschsignale von der Prozessorschicht vorgesehen und stellt den Elementen der Prozessorschicht keinen Strom bereit.

公开(公告)号：GB2498892B

公开(公告)日：2014-08-20

申请号：GB201308320

申请日：2011-10-21

Applicant: IBM

Inventor： HUBER ANDREAS ,  HARRER HUBERT ,  NIGGEMEIER TIM ,  SUPPER JOCHEN ,  MICHEL BRUNO ,  BRUNSCHWILER THOMAS J ,  PAREDES STEPHAN ,  BAROWSKI HARRY

IPC: H01L25/065 ,  H01L25/10

公开(公告)号：GB2458721A

公开(公告)日：2009-09-30

申请号：GB0820513

申请日：2008-11-10

Applicant: IBM

Inventor： BAROWSKI HARRY ,  NIGGEMEIER TIM ,  JAESCHKE CHRISTOPH ,  WAKUNDA JUERGEN

IPC: G06F17/50 ,  G06F1/32

Abstract: The invention relates to a method and a system for verifying a microprocessor design with multiple power gate domains (21, 22). The checks are done via structural checks of a hierarchical netlist of the design and use signal based traversion. Specifically, the invention encompasses an identification of the power gate domains (21, 22) within the design, defining traversal trajectories along signal interconnections (61, 61', 61'') between power gate domains (21, 22) and determining compliance of interconnections between starting points (71. 71', 71'') and end points (72, 72', 72'') of said trajectories with respect to a set of design rules.

公开(公告)号：GB2498892A

公开(公告)日：2013-07-31

申请号：GB201308320

申请日：2011-10-21

Applicant: IBM

Inventor： HUBER ANDREAS ,  HARRER HUBERT ,  NIGGEMEIER TIM ,  SUPPER JOCHEN ,  MICHEL BRUNO ,  BRUNSCHWILER THOMAS J ,  PAREDES STEPHAN ,  BAROWSKI HARRY

IPC: H01L25/065 ,  H01L25/10

Abstract: A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

公开(公告)号：GB2498310A

公开(公告)日：2013-07-10

申请号：GB201307552

申请日：2011-10-21

Applicant: IBM

Inventor： BAROWSKI HARRY ,  HUBER ANDREAS ,  HARRER HUBERT ,  NIGGEMEIER TIM ,  SUPPER JOCHEN ,  MICHEL BRUNO ,  BRUNSCHWILER THOMAS ,  PAREDES STEPHAN

IPC: H01L23/50 ,  H01L23/36

Abstract: A mechanism is provided for integrated power delivery and distribution via a heat sink. The mechanism comprises a processor layer coupled to a signaling and input/output (I/O) layer via a first set of coupling devices and a heat sink coupled to the processor layer via a second set of coupling devices. In the mechanism, the heat sink comprises a plurality of grooves on one face, where each groove provides either a path for power or a path for ground to be delivered to the processor layer. In the mechanism, the heat sink is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism and the signaling and I/O layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the process layer.

公开(公告)号：GB2458721B

公开(公告)日：2012-01-11

申请号：GB0820513

申请日：2008-11-10

Applicant: IBM

Inventor： BAROWSKI HARRY ,  NIGGEMEIER TIM ,  JAESCHKE CHRISTOPH ,  WAKUNDA JUERGEN

IPC: G06F17/50 ,  G06F1/32

公开(公告)号：GB2456363A

公开(公告)日：2009-07-15

申请号：GB0820474

申请日：2008-11-10

Applicant: IBM

Inventor： BAROWSKI HARRY ,  NIGGEMEIER TIM ,  GEMMEKE TOBIAS

IPC: G06F1/32 ,  G06F17/50

Abstract: The invention relates to a method and a system for analyzing and optimizing clock gating within a functional unit of an electronic design with a plurality of latches (10). In this method, a simulation of the design is performed to obtain clock activation signals (50) and data latch output signals (60) of said latches (10); by analyzing these data (50, 60) for the latches (10) at various clock cycles (ti), clock cycles (ti) are extracted when a given latch (10) may be clock gated. Specifically, the method comprises the steps of generating a latch clock activation matrix (100) containing clock activation and data switching information for each latch (10), identifying potentially unnecessary clock activity and deriving an improved clock gating design by eliminating unnecessary clock activity. Simulations can be performed on a HDL model. A verification check may be employed.

公开(公告)号：GB2516864A

公开(公告)日：2015-02-11

申请号：GB201313825

申请日：2013-08-02

Applicant: IBM

Inventor： NIGGEMEIER TIM ,  BAROWSKI HARRY

IPC: G06F9/38

Abstract: A processor 100 comprises a writeback buffer 110 in a dataflow between an execution unit 104 and a register file 108 of the processor. The buffer stores a result of a first completed instruction of the execution unit when the first completed instruction attempts to write back to the register file at the same processor time as a second completed instruction of another execution unit 106, e.g. during the same processor cycle. The processor also comprises an instruction scheduling unit 101 comprising a buffer full indicator (622, fig. 6), wherein an execution unit result is written back from the writeback buffer in response to the buffer full indicator. The processor also comprises a merging means to detect and combine a first execution unit instruction of the processors instruction stream (402, fig. 4) with a second execution unit instruction when the second instruction has an input data dependency to a result of the first instruction. The instruction sequencing unit comprises a pair detection means (442, fig. 4) and a pair issuing means, wherein the pair detection means is adapted to detect that the first execution unit instruction which is ready for issue is paired with the second execution unit instruction.