1.
    发明专利
    未知

    公开(公告)号:DE3483929D1

    公开(公告)日:1991-02-21

    申请号:DE3483929

    申请日:1984-07-05

    Applicant: IBM

    Abstract: A high speed multiplier unit (29) for multiplying both fixed point and floating point fractioned operands. This multiplier unit is a system level functional unit which allows floating point and fixed point operations to be performed directly. In addition to multiplication, the multiplier unit performs exponent calculation, postnormalization, and error detection. The multiplier unit also provides for overlapped loading of variable lengths operands.

    2.
    发明专利
    未知

    公开(公告)号:DE3485728D1

    公开(公告)日:1992-06-25

    申请号:DE3485728

    申请日:1984-03-30

    Applicant: IBM

    Abstract: A bypass apparatus in a computer system is disclosed. The computer system includes a central storage facility for storing various instructions to be executed, an instruction register for storing an instruction being executed, and an instruction buffer, interconnected between the central storage facility and the instruction register, for temporarily storing the next instructions to be executed following execution of the instruction stored in the instruction register. A bypass path interconnects the cache to the instruction register for bypassing the instruction buffer when certain special instructions are being executed, such as an EXECUTE instruction. Consequently, the contents of the instruction buffer are not lost or destroyed as a result of execution of the special instruction. The computer system further includes an execute register interconnected between the central storage facility and the instruction register for storing one or more bytes of the instruction being executed when the byte-length of the instruction is greaterthan the byte-length of the instruction register which stores said instruction.

    4.
    发明专利
    未知

    公开(公告)号:BR8401796A

    公开(公告)日:1985-03-19

    申请号:BR8401796

    申请日:1984-04-17

    Applicant: IBM

    Abstract: A high speed multiplier unit (29) for multiplying both fixed point and floating point fractioned operands. This multiplier unit is a system level functional unit which allows floating point and fixed point operations to be performed directly. In addition to multiplication, the multiplier unit performs exponent calculation, postnormalization, and error detection. The multiplier unit also provides for overlapped loading of variable lengths operands.

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