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    1.
    发明专利
    未知

    公开(公告)号：DE3750520D1

    公开(公告)日：1994-10-20

    申请号：DE3750520

    申请日：1987-04-14

    Applicant: IBM

    Inventor： NGAI CHUCK HONG ,  WATKINS GERALD JOSEPH

    IPC: G06F9/22 ,  G06F15/16 ,  G06F17/16

    Abstract: A method for optimizing performance in a fixed clock rate computer system. A control word is provided having a control portion for operational instructions and a programmable timing portion. The programmable timing portion includes a value representative of the sum of execution time and inter-execution delay time. A counter (22i) is provided for receiving the value representative of the execution and inter-execution times. The counter is capable of generating a signal (EOS) to indicate an end of decrementing operation. The operational instructions are executed simultaneously with the processing of the time value in the counter so that a subsequent instruction is executed only when an end of operation signal is received from the counter.

    2.
    发明专利
    未知

    公开(公告)号：DE3686828D1

    公开(公告)日：1992-11-05

    申请号：DE3686828

    申请日：1986-02-14

    Applicant: IBM

    Inventor： NGAI CHUCK HONG ,  WATKINS GERALD JOSEPH

    IPC: G06F17/16 ,  G06F15/80 ,  G06F15/347 ,  G06F15/76

    Abstract: A parallel vector processor includes a plurality of vector registers, each vector register being subdivided into a plurality of smaller registers. A vector is stored in each vector register, the vector has a plurality of elements. The elements of the vector are assigned for storage in the smaller registers of the vector register. In the parallel vector processor, assume that each vector register is subdivided into M smaller registers. The first successive M elements of an N element vector are assigned for storage in the M smaller registers of the vector register. An element processor is connected to each smaller register. Therefore, the first successive M elements of the N element vector are processed by the element processors 1 through M. The second successive M elements of the N element vector are assigned for storage in the same M smaller registers. The third successive M elements of the N element vector are assigned for storage in the M smaller registers. The second and third successive M elements of the N element vector are each processed by the element processors 1 through M. As a result, if the elements of a vector must be processed sequentially, when a second element, stored in a smaller register, is ready for processing by an element processor, the processing of the second element need not wait the completion of the processing of a first element stored in the same vector register.

    3.
    发明专利
    未知

    公开(公告)号：DE69519886T2

    公开(公告)日：2001-06-21

    申请号：DE69519886

    申请日：1995-03-14

    Applicant: IBM

    Inventor： CHENEY DENNIS PHILLIP ,  CONZOLA VINCENT CHARLES ,  NGAI CHUCK HONG ,  PFEIFFER RICHARD THOMAS

    IPC: H04N7/32 ,  G06T9/00 ,  H04N7/26 ,  H04N7/50

    Abstract: Disclosed is a digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals. The decoder system includes a FIFO Data Buffer, a RAM having (1) a compressed, encoded Data Buffer and (2) a data portion for storing decompressed digital video buffer data. A Memory Management Unit is provided for managing the RAM. The decoder has a decoder processor that includes a Variable Length Code Decoder for receiving encoded data, a (2,3,3) parallel counter based Inverse Quantizer for dequantizing the decoded data, an Inverse Discrete Cosine Transform Decoder for transforming the dequantized, decoded data into Intrapictures, Predicted Pictures, and Bidirectional predicted Pictures, a Motion Compensator for receiving Intrapictures and other information from the RAM, and error functions, and forming motion compensated predicted pictures therefrom for return to the RAM, a Display Unit to output motion compensated pictures from the RAM, and a reduced instruction set Controller to control the Memory Management Unit, the Variable Length Code Decoder, the Inverse Quantizer, the Inverse Discrete Cosine Transform Decoder, the Motion Compensator, and the Display Unit.

    5.
    发明专利
    未知

    公开(公告)号：DE3485728D1

    公开(公告)日：1992-06-25

    申请号：DE3485728

    申请日：1984-03-30

    Applicant: IBM

    Inventor： BURGER MARK EDWARD ,  GEORGE STEVEN LEE ,  NGAI CHUCK HONG

    IPC: G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38

    Abstract: A bypass apparatus in a computer system is disclosed. The computer system includes a central storage facility for storing various instructions to be executed, an instruction register for storing an instruction being executed, and an instruction buffer, interconnected between the central storage facility and the instruction register, for temporarily storing the next instructions to be executed following execution of the instruction stored in the instruction register. A bypass path interconnects the cache to the instruction register for bypassing the instruction buffer when certain special instructions are being executed, such as an EXECUTE instruction. Consequently, the contents of the instruction buffer are not lost or destroyed as a result of execution of the special instruction. The computer system further includes an execute register interconnected between the central storage facility and the instruction register for storing one or more bytes of the instruction being executed when the byte-length of the instruction is greaterthan the byte-length of the instruction register which stores said instruction.

    7.
    发明专利
    未知

    公开(公告)号：DE69519886D1

    公开(公告)日：2001-02-22

    申请号：DE69519886

    申请日：1995-03-14

    Applicant: IBM

    Inventor： CHENEY DENNIS PHILLIP ,  CONZOLA VINCENT CHARLES ,  NGAI CHUCK HONG ,  PFEIFFER RICHARD THOMAS

    IPC: H04N7/32 ,  G06T9/00 ,  H04N7/26 ,  H04N7/50

    Abstract: Disclosed is a digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals. The decoder system includes a FIFO Data Buffer, a RAM having (1) a compressed, encoded Data Buffer and (2) a data portion for storing decompressed digital video buffer data. A Memory Management Unit is provided for managing the RAM. The decoder has a decoder processor that includes a Variable Length Code Decoder for receiving encoded data, a (2,3,3) parallel counter based Inverse Quantizer for dequantizing the decoded data, an Inverse Discrete Cosine Transform Decoder for transforming the dequantized, decoded data into Intrapictures, Predicted Pictures, and Bidirectional predicted Pictures, a Motion Compensator for receiving Intrapictures and other information from the RAM, and error functions, and forming motion compensated predicted pictures therefrom for return to the RAM, a Display Unit to output motion compensated pictures from the RAM, and a reduced instruction set Controller to control the Memory Management Unit, the Variable Length Code Decoder, the Inverse Quantizer, the Inverse Discrete Cosine Transform Decoder, the Motion Compensator, and the Display Unit.

    8.
    发明专利
    未知

    公开(公告)号：DE3750520T2

    公开(公告)日：1995-04-06

    申请号：DE3750520

    申请日：1987-04-14

    Applicant: IBM

    Inventor： NGAI CHUCK HONG ,  WATKINS GERALD JOSEPH

    IPC: G06F9/22 ,  G06F15/16 ,  G06F17/16

    Abstract: A method for optimizing performance in a fixed clock rate computer system. A control word is provided having a control portion for operational instructions and a programmable timing portion. The programmable timing portion includes a value representative of the sum of execution time and inter-execution delay time. A counter (22i) is provided for receiving the value representative of the execution and inter-execution times. The counter is capable of generating a signal (EOS) to indicate an end of decrementing operation. The operational instructions are executed simultaneously with the processing of the time value in the counter so that a subsequent instruction is executed only when an end of operation signal is received from the counter.

    9.
    发明专利
    未知

    公开(公告)号：DE3686828T2

    公开(公告)日：1993-04-01

    申请号：DE3686828

    申请日：1986-02-14

    Applicant: IBM

    Inventor： NGAI CHUCK HONG ,  WATKINS GERALD JOSEPH

    IPC: G06F17/16 ,  G06F15/80 ,  G06F15/347 ,  G06F15/76

    Abstract: A parallel vector processor includes a plurality of vector registers, each vector register being subdivided into a plurality of smaller registers. A vector is stored in each vector register, the vector has a plurality of elements. The elements of the vector are assigned for storage in the smaller registers of the vector register. In the parallel vector processor, assume that each vector register is subdivided into M smaller registers. The first successive M elements of an N element vector are assigned for storage in the M smaller registers of the vector register. An element processor is connected to each smaller register. Therefore, the first successive M elements of the N element vector are processed by the element processors 1 through M. The second successive M elements of the N element vector are assigned for storage in the same M smaller registers. The third successive M elements of the N element vector are assigned for storage in the M smaller registers. The second and third successive M elements of the N element vector are each processed by the element processors 1 through M. As a result, if the elements of a vector must be processed sequentially, when a second element, stored in a smaller register, is ready for processing by an element processor, the processing of the second element need not wait the completion of the processing of a first element stored in the same vector register.

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