公开(公告)号：JP2008021314A

公开(公告)日：2008-01-31

申请号：JP2007182029

申请日：2007-07-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GERMANN PHILIP RAYMOND ,  BORKENHAGEN JOHN M ,  GERALD KEITH BARTLEY ,  HOVIS WILLIAM PAUL

IPC: G06F12/06 ,  G06F12/00 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F13/161 ,  G06F12/08 ,  G06F12/122

Abstract: PROBLEM TO BE SOLVED: To provide a multilevel memory architecture with data prioritization. SOLUTION: In a method of controlling computer-readable memory that includes a plurality of memory locations, a usage frequency of a data unit stored in a first memory location is determined. The data unit is moved to a second memory location different from the first memory location that is selected based on a correspondence between a known latency of the second memory location and the usage frequency of the data unit, in which the second memory location is the primary data storage location for the data unit. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供具有数据优先级的多级存储器架构。 解决方案：在控制包括多个存储器位置的计算机可读存储器的方法中，确定存储在第一存储器位置中的数据单元的使用频率。 数据单元被移动到不同于基于第二存储器位置的已知等待时间与数据单元的使用频率之间的对应关系而选择的第一存储器位置的第二存储器位置，其中第二存储器位置是主要的 数据单元的数据存储位置。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008234662A

公开(公告)日：2008-10-02

申请号：JP2008074311

申请日：2008-03-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GERMANN PHILIP RAYMOND ,  BORKENHAGEN JOHN M ,  BECKER DARRYL J ,  BARTLEY GERALD KEITH ,  HOVIS WILLIAM PAUL

IPC: G06F12/06 ,  G06F1/32 ,  G11C11/401 ,  G11C11/407

CPC classification number: Y02D10/13

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for implementing power saving in addressing of a DRAM device. SOLUTION: A random access memory device includes an array of individual memory cells arranged into rows and columns, and each memory cell has a corresponding access device. Assuming N as the number corresponding to the number of independently accessible partitions of the array, each row of the array further includes a corresponding plurality of N word lines, and each access device in a given row is coupled to only one of the N word lines of the rows. An address decoder communicating with the array receives a plurality of row address bits, and determines which of the N partitions in a requested row must be accessed on the requested row identified by the row address bits, and does not activate the access device within the selected row but not within the partition to be accessed. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在DRAM设备的寻址中实现省电的结构和方法。 解决方案：随机存取存储器件包括排列成行和列的各个存储单元的阵列，并且每个存储单元具有对应的存取设备。 假设N为与阵列的独立可访问分区的数量相对应的数字，阵列的每一行还包括相应的多个N个字线，并且给定行中的每个访问设备仅耦合到N个字线中的一个 的行。 与阵列通信的地址解码器接收多个行地址位，并且确定在所请求的行中必须在由行地址位标识的所请求的行上访问所述N个分区中的哪一个，并且不激活所选行中的访问设备 行，但不在要访问的分区内。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：DE602008002436D1

公开(公告)日：2010-10-14

申请号：DE602008002436

申请日：2008-06-25

Applicant: IBM

Inventor： BARTLEY GERALD KEITH ,  BORKENHAGEN JOHN MICHAEL ,  GERMANN PHILIP RAYMOND

IPC: G06F13/16