公开(公告)号：CA1233233A

公开(公告)日：1988-02-23

申请号：CA510245

申请日：1986-05-28

Applicant: IBM

Inventor： HONG JU-HI J

IPC: H04J9/00 ,  G06F11/10 ,  H03M5/02 ,  H03M13/00 ,  H03M13/37 ,  H03M13/45 ,  H04L1/24 ,  H04L25/06 ,  H04L25/497 ,  H04N7/16

Abstract: ERROR CORRECTION SCHEME An error correcting scheme for processing data which is transmitted on a broadcast and/or CATV network and utilizes the IEEE 802.4 three-level duobinary AM/PSK (phase shift keying) coding format. The error correcting scheme utilizes two thresholders. One of the thresholders makes data (1 or 0) decisions while the other thresholder makes non-data or no non-data (non-data) decisions. Pattern matching and windowing are used to detect non-data symbols which are corrected if the non-data symbols deviate from a predetermined pattern. The template used in the pattern matching is determined from the state of a demodulator. Background of the Invention (1) Field of the Invention The invention relates to the detection and correction of errors in information processing and, more particularly, to detection and correction of errors in signals transmitted on a broadband network utilizing a three-level duobinary AM/PSK coding format. (2) Prior Art Error detecting and correcting techniques for processing information are well known in the prior art. Most error detecting and correcting techniques are directly related to the type of coding technique used to handle the data. U.S. Patent 4,118,686 describes an isolated (single) error

公开(公告)号：FR2311450A1

公开(公告)日：1976-12-10

申请号：FR7610358

申请日：1976-04-01

Applicant: IBM

Inventor： GINDI ABRAHAM M ,  HONG JU-HI J ,  STELZENMULLER WILLIAM K

IPC: H03K5/00 ,  H03M5/12 ,  H03L7/00 ,  H04J3/06 ,  H04L5/22 ,  H04L7/00 ,  H04L7/033 ,  H04L25/40 ,  H04L25/49 ,  H04Q11/04 ,  H03K5/153

Abstract: An improved clock retiming system for pulse coded data is provided in which the clock signals are extracted from the encoded data and first and second signals of the same amplitude and frequency but of different phase are generated from the clock signals. First and second amplifiers having variable gains provide amplification for the first and second signals, respectively. The first and second amplified signals are summed to produce a third signal having a phase which is a function of the relative amplitudes of the first and second amplified signals. The original pulse encoded data is sampled with the third signal to produce the retimed data output. The original pulse encoded data is also utilized to sample the third signal. The resulting signal is filtered to provide a DC voltage feedback error signal indicative of the phase difference between the third signal and the original pulse encoded data. This feedback signal is translated into a pair of complementary signals forming inputs to the first and second amplifiers, respectively, to vary the variable gains thereof, oppositely thereby adjusting the phase of the third signal to correspond to the phase of the original pulse encoded data.