1.
    发明专利
    未知

    公开(公告)号:FR2410337A1

    公开(公告)日:1979-06-22

    申请号:FR7828296

    申请日:1978-09-26

    Applicant: IBM

    Inventor: GLADSTEIN LEO A

    Abstract: The problem of a race condition in the precharged drain type FET read only storage circuits is avoided in the invention disclosed herein, by applying the bit decode signal to the source of the array device, so that the drain cannot be discharged through the FET array device unless both the bit line connected to the source and word line connected to the gate have on-signals. Thus, the memory circuit can be operated in a faster cycle because the word and bit signals may be made coincident.

    SUBSTRATE POLARISATION VOLTAGE GENERATOR CIRCUIT

    公开(公告)号:DE2961322D1

    公开(公告)日:1982-01-14

    申请号:DE2961322

    申请日:1979-08-23

    Applicant: IBM

    Abstract: An FET substrate voltage generator circuit is disclosed for converting a single power supply and ground potential to a negative potential having an absolute value whose magnitude is greater than the power supply potential and applying that potential to the substrate of an integrated circuit upon which it is formed. The circuit dissipates less power per unit of current supplied by the circuit and occupies less space than do prior art circuits. The circuit applies the principle of voltage doubling to a first capacitor to achieve the desired voltage magnitude across a second capacitor and then applies the principle of a.c. coupling to that second capacitor connected through an impedance to the first capacitor, to achieve the desired polarity inversion for the substrate voltage to be generated. This circuit provides the current generating capacity necessary to drive the substrate to a negative voltage and sink the required current so as to maintain the substrate at an adequate negative bias.

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